Kevin Stawiasz

High‐resolution scanning SQUID microscope

We have combined a novel low temperature positioning mechanism with a single‐chip miniature superconducting quantum interference device (SQUID) magnetometer to form an extremely sensitive new magnetic microscope, with a demonstrated spatial resolution of ∼10 μm. The design and operation of this scanning SQUID microscope will be described. The absolute calibration of this instrument with an ideal point source, a single vortex trapped in a superconducting film, will be presented, and a representative application will be discussed.

Fluctuation limits & scaling opportunities for CMOS SRAM cells

Fundamental limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring the local stochastic distributions of read, write and retention DC margins of 65nm PDSOI CMOS SRAM cells. DC measurements show, for the first time, the write operation to be more fluctuation limited. Measurements also reveal fundamental insights into terminal voltage dependencies of the fluctuations of cell storage node voltages - observations that are engaged to increase cell immunity to fluctuations by several orders of magnitude by biasing the cell terminal voltages appropriately

A fully-integrated switched-capacitor 2∶1 voltage converter with regulation capability and 90% efficiency at 2.3A/mm 2

A switched-capacitor DC-DC voltage converter in 45nm SOI CMOS leverages on-chip trench capacitors to achieve 90% efficiency at an output of 2.3A/mm2 for 2V-to-0.95V conversion at 100MHz. Operation in step-up and step-down modes is demonstrated. Combined with stacked voltage domains, self-regulation capability enables further efficiency improvement.

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing

Fluctuation limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring local stochastic distributions of 65-nm PDSOI CMOS SRAM cell storage node voltages during read, write, and retention modes of operation. These measurements reveal insights into terminal voltage dependencies of cell margin distributions - observations that are engaged to increase cell immunity to random VT fluctuations by several orders of magnitude by biasing the cell terminal voltages dynamically with a read-write asymmetry. Combinations of circuit techniques implementing these dynamic cell biasing schemes are demonstrated in a 9 kb times74 b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST. Measurements demonstrate these techniques to enable VMIN reductions of over 200 mV - lowering measured VMIN to 0.54 V and 0.38 V/0.50 V for single and dual VDD implementations, respectively. The techniques consume a 10%-12% overhead in area, impact performance marginally (<5%) and also enable over 50% reduction in cell leakage.

A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs

Most existing power gating structures provide only one power-saving mode. We propose a novel power gating structure that supports both a cutoff mode and an intermediate power-saving and data-retaining mode. Experiments with test structures fabricated in 0.13-mum CMOS bulk technology show that our power gating structure yields an expanded design space with more power-performance tradeoff alternatives.

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8 TM microprocessor

Integrated voltage regulator modules (iVRMs) [1] provide a cost-effective path to realizing per-core dynamic voltage and frequency scaling (DVFS), which can be used to optimize the performance of a power-constrained multi-core processor. This paper presents an iVRM system developed for the POWER8™ microprocessor, which functions as a very fast, accurate low-dropout regulator (LDO), with 90.5% peak power efficiency (only 3.1% worse than an ideal LDO). At low output voltages, efficiency is reduced but still sufficient to realize beneficial energy savings with DVFS. Each iVRM features a bypass mode so that some of the cores can be operated at maximum performance with no regulator loss. With the iVRM area including the input decoupling capacitance (DCAP) (but not the output DCAP inherent to the cores), the iVRMs achieve a power density of 34.5W/mm2, which exceeds that of inductor-based or SC converters by at least 3.4× [2].

A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS

An 8T SRAM fabricated in 45 nm SOI CMOS exhibits voltage scalable operation from 1.2V down to 0.57V with access times from 400 ps to 3.4 ns. Timing variation and the challenge of low voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a regenerative global bitline scheme. Finally, a data retention voltage sensor has been developed to predict the mismatch-limited minimum standby voltage without corrupting the contents of the memory.

Minimizing inductive noise in system-on-a-chip with multiple power gating structures

A multiple power domain strategy in which each power domain has an independent power gating structure is an effective means for reducing leakage power consumption in a system-on-a-chip. During an individual power gating structure power-mode transition, however, serious inductive noise is introduced that may affect normal operation of neighboring circuits. We present a novel power gating structure in which inductive noise is reduced through gradual turn-on and turn-off its sleep transistor. Experimental simulation results with PowerSpice fixtured in different package models demonstrate the effectiveness of the proposed power gate switching noise reduction technique.

High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor

As microprocessor speeds approach 1 GHz and beyond the difficulties of at-speed testing continue to increase. In particular, automated test equipment which operates at these frequencies is very limited. This paper discusses a design-for-test method which serializes parallel circuit inputs and de-serializes circuit outputs to achieve 1 GHz operation on test equipment operating at frequencies below 100 MHz. This method has been used to successfully characterize the operation of a 1 GHz microprocessor chip.

Design and applications of a scanning SQUID microscope

The scanning SQUID (Superconducting Quantum Interference Device) microscope is an extremely sensitive instrument for imaging local magnetic fields. The authors describe one such instrument which combines a novel pivoting lever mechanism for coarse-scale imaging with a piezoelectric tube scanner for fine-scale scans. The magnetic field sensor is an integrated miniature SQUID magnetometer. This instrument has a demonstrated magnetic field sensitivity of <10{sup {minus}6} gauss/{radical}Hz at a spatial resolution of {approximately}10 {micro}m. The design and operation of this scanning SQUID microscope are described, and several illustrations of the capabilities of this technique are presented. The absolute calibration of this instrument with an ideal point source, a single vortex trapped in a superconducting film, is shown. The use of this instrument for the first observation of half-integer flux quanta, in tricrystal thin-film rings of YBa{sub 2}Cu{sub 3}O{sub 7{minus}{delta}}, is described. The half-integer flux quantum effect is a general test of the symmetry of the superconducting order parameter. One such test rules out symmetry-independent mechanisms for the half-integer flux quantum effect, and proves that the order parameter in YBa{sub 2}Cu{sub 3}O{sub 7{minus}{delta}} has lobes and nodes consistent with d-wave symmetry.