B. A. Chen

Resistive Memory Switching of

Poly crystalline CuxO films produced by plasma oxidation are investigated for nonvolatile memory applications. Reversible bistable resistive switching from a high-resistance state to a low-resistance state, and vice versa, is observed in an integrated Al/CuxO/Cu structure under voltage sweeping. More than 3000 repetitive cycles are observed in 180-mum memory devices with an on/off ratio of ten times. Data testing shows that the devices meet the ten-year retention requirement for the storage of programmed logic signals.

\hbox{Cu}_{x}\hbox{O}

For the first time, we report that the copper oxide (CuxO) based resistive random access memory (RRAM) cell can achieve 104 cycles (i.e. ~10x better) as a new record as well as elimination of the initial ¿forming¿ than reported in literature. The copper oxide is integrated in MIM (metal-insulator-metal) structure and is grown by plasma oxidation of Cu substrate, with CuO near upper surface and graded CuxO (i.e. increasingly Cu rich or O-vacancies rich) toward the Cu substrate. A thinner CuO upper layer can eliminate ¿forming¿ process and, for in turn, greatly enhance the endurance of resistive switching by eliminating the damage during the ¿forming¿ process.

Films for a Nonvolatile Memory Application

The forming process, which is the first transition from fresh state to low resistance state, was investigated in CuxO memory films prepared by plasma-induced oxidation. X-ray photoelectron spectroscopy investigation of surface chemical bonds of CuxO films and Auger electron spectroscopy depth spectra show that the formation of a highly resistive CuO layer on the CuxO surface is the main reason for the requirement of a large forming voltage. After selectively deoxidizing the CuO into Cu2O, the need for the forming process disappears.

Enhancement of endurance for Cu x O based RRAM cell

Wide dispersions of memory switching parameters are observed in resistive random access memory based on Al/CuxO/Cu structure. Moreover, the switching instability induced by these dispersions is studied. In this letter, a ramped-pulse series operation method is put forward, which can improve switching stability and cycling endurance remarkably. A method for minimizing the dispersion of Vreset by optimizing the amplitude of pulse is proposed further. The write-read-erase-read operations can be over 8 times103 cycles without degradation by using the new operation mode. The role of Joule heating behind this behavior of Al/CuxO/Cu device is discussed.

Forming Process Investigation of

Heterojunction diodes are fabricated using p-type Ge2Sb2Te5 and low doped n-type silicon wafer. Rectification is observed with a ratio of forward-to-reverse current as high as 104 and 103 for crystal-Ge2Sb2Te5/n-Si junction and amorphous-Ge2Sb2Te5/n-Si junction, respectively. The approximate equilibrium energy-band diagrams for both crystal-Ge2Sb2Te5/n-Si heterojunction diodes and amorphous-Ge2Sb2Te5/n-Si heterojunction diodes are proposed to explain the properties of the p-Ge2Sb2Te5/n-Si heterojunction diode. Properties of a p-n heterojunction diode based on Ge2Sb2Te5 are proposed to apply in 0T1R cross-point structure array for reliable read operation and for decreasing the sneaking current.

\hbox{Cu}_{x} \hbox{O}

We propose an asymmetric write algorithm of step-down set/step-up reset without verify for the first time. The demonstration is carried out on a 128Kb test macro of AlO_x/WO_x bi-layer ReRAM fabricated based on 0.18μm logic process. The set and reset energy per bit are reduced by 34% and 20% respectively. The set and reset access time decrease by 54% and 32% respectively. The mean value of endurance distribution is improved by 2 orders of magnitude from 10⁷ to 10⁹. R_on and R_off retention failure rate is reduced by 88% and 71% respectively. R_off/R_on window enlarges from 25× to 180×. The reliability improvements are attributed to refinement of CF shape and size by the step-down set algorithm.

Memory Films

A nonvolatile static random access memory (NVSRAM) cell with two back-up CuxO memory devices is proposed in this paper. The manufacturing process is compatible with the standard CMOS process. By adopting a dynamic supply voltage scheme, the proposed cell can work correctly in four different operation modes. Compared with the standard SRAM cell, the proposed cell offers non-volatile storage which allows the unused blocks of SRAM to be powered down to save energy.

Improvement of Resistive Switching in

We propose co-optimization of VRRAM cell structure and array architecture as well as IR-drop-aware read/write algorithms to overcome issues of disturbance and IR drop from long wire. A bi-directional diode (2D) access device is combined with one resistor to form 2D1R cell. A dummy reference plane is inserted into array to set up the same IR drop path of reference cell with that of selected cell. Consequently, the same IR drop effect can be cancelled during read. The model for disturbance analysis is put forward. Voltage dropped on un-selected bit lines is the key parameter to suppress set disturbance. Set disturbance is significantly suppressed even when number of RRAM layers increases to 64. Set voltage has to meet corresponding requirements in order to minimize the disturbance risk.

\hbox{Cu}_{x} \hbox{O}

A true random number generator using write speed variation of oxide-based RRAM is proposed for the first time. The signal of this physical unclonable function (PUF) is strong with long duration to be easily and accurately captured by simple circuit, of which the advantage is attributed to the mechanism that the speed variation amplifies the fluctuation of oxygen vacancy trap and de-trap. Some function parts of normal RRAM IP can be reused as entropy source cells and implementation circuit. The variation of write end point is monitored by a self-adaptive write drive circuit to trig a counter, and then serialized into a bit stream. The test chips, which are AlOx/WOx bilayer back-end RRAM fabricated in 0.18 Um logic process, passed all NIST tests with advantages of small area, low power, and not using post-processor corrector. Enough bits can be generated within the endurance limitation to ensure usual Internet of Things (IoT) security application.

Using New RESET Mode

Abstract Domain wall memory (DMW) or Racetrack memory (RM) has attracted great attention for its enormous capacity. However, the array architecture are not clear. Prior arts have very low capacity utilization (only 50 % ) as well as high shift voltage. This paper proposed a 1 transistor X cells (1TXC) array architecture based on X-bar cell structure for 3D DWM, which realizes 100 % capacity utilization, 50 % shift power reduction and attains simplified peripheral decoding circuit as well as cost efficiency. Further, a corresponding anti-disturbance read operation algorithm is put forward, which can inhibit misread problem caused by sneaking current.