Erik Haralson

Self-heating effects in a BiCMOS on SOI technology for RFIC applications

Self-heating in a 0.25 /spl mu/m BiCMOS technology with different isolation structures, including shallow and deep trenches on bulk and silicon-on-insulator (SOI) substrates, is characterized experimentally. Thermal resistance values for single- and multifinger emitter devices are extracted and compared to results obtained from two-dimensional, fully coupled electrothermal simulations. The difference in thermal resistance between the investigated isolation structures becomes more important for transistors with a small aspect ratio, i.e., short emitter length. The influence of thermal boundary conditions, including the substrate thermal resistance, the thermal resistance of the first metallization/via layer, and the simulation structure width is investigated. In the device with full dielectric isolation-deep polysilicon-filled trenches on an SOI substrate-accurate modeling of the heat flow in the metallization is found to be crucial. Furthermore, the simulated structure must be made wide enough to account for the large heat flow in the lateral direction.

Base resistance scaling for SiGeC HBTs with a fully nickel-silicided extrinsic base

A novel SiGeC HBT process with a quasi-self-aligned emitter-base architecture and a fully nickel-silicided extrinsic base region has been developed. A very low total base resistance R/sub B/ was achieved along with simultaneous NiSi formation on the polycrystalline emitter and collector regions. Uniform silicide formation was obtained across the wafer, and the resistivity of the Ni(SiGe:C) silicide layer was 24 /spl mu//spl Omega//spl middot/cm. About 50-100 nm of lateral growth of silicide underneath the emitter pedestal was observed. DC and HF results with balanced f/sub T//f/sub MAX/ values of 41/42 GHz were demonstrated for 0.5/spl times/10/spl mu/m/sup 2/ transistors.

High Frequency Performance of SiGeC HBTs with Selectively & Non-Selectively Grown Collector

Two high-frequency heterojunction bipolar transistor (HBT) architectures based on SiGeC have been fabricated and characterized. Different collector designs were applied either by using selective epitaxial growth doped with phosphorous or by nonselective epitaxial growth doped with arsenic. Both designs have a nonselectively deposited SiGeC base doped with boron and a poly-crystalline emitter doped with phosphorous. Both HBT designs exhibit similar electrical characteristics with a peak DC current gain of around 1600 and a BVCEO of 1.8V. The cut-off frequency (fT) and maximum frequency of oscillation (fmax) vary from 40–80GHz and 15–30GHz, respectively, depending on lateral design relations. Good high frequency performance for a device with a selectively grown collector is demonstrated for the first time.

As- or P-Doped Si Layers Grown by RPCVD for Emitter Application in SiGeC HBTs

A new module for the emitter formation in a bipolar transistor is presented. Arsenic- or phosphorus-doped polycrystalline silicon layer for the emitter formation is deposited in a reduced pressure ...