B. Kaczer

Consistent model for short-channel nMOSFET after hard gate oxide breakdown

Dissimilar post-hard-breakdown nMOSFET characteristics are consistently explained by the location of a constant-size breakdown path. Device simulations with the breakdown path modeled as a narrow inclusion of highly doped n-type silicon well reproduce all postbreakdown nFET characteristics, including the substrate current behavior, for both gate-to-substrate and gate-to-extension breakdowns. An equivalent circuit describing the gate current in an nFET after hard gate-oxide breakdown is proposed.

Relation between breakdown mode and breakdown location in short channel NMOSFETs and its impact on reliability specifications

A method to determine the breakdown position in short channel nMOSFETs is introduced. We find that soft breakdown occurs exclusively in the transistor channel while the hardest circuit killing breakdowns occur above the source and drain extension regions. Since these breakdowns make up only a small fraction of all breakdowns, a relaxation of the reliability specification is possible.

High performance Ge pMOS devices using a Si-compatible process flow

Ge pMOS mobilities up to 358 cm²/Vs are demonstrated using a Si-compatible process flow without the incorporation of strain. EOT is approximately 12 Aring with a gate leakage less than 0.01 A/cm ² at V_t+ 0.6 V. Ge transistors are characterized with gate lengths ranging from 10 mum down to 0.125 mum, the shortest ever reported. We also present the best Ge pMOS drain current to date of 790 muA/mum at V_gt = V_d = -1.5V for an L_g of 0.19 mum

Trap Spectroscopy by Charge Injection and Sensing (TSCIS): A quantitative electrical technique for studying defects in dielectric stacks

Trap spectroscopy by charge injection and sensing (TSCIS) is a new, fast and powerful material analysis technique that provides detailed information on the trap density profile and trap energy level in dielectric materials. We show the measurement principle and explain the data analysis. The technique is applied to a number of example materials: SiO₂, Al₂O₃, and Si₃N₄. We show that TSCIS has excellent resolution and is capable of distinguishing between different process-variations.

Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs

We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different technologies, based on which we propose a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on the electrical characteristic of deeply scaled transistors. Among the considered technologies, nanoscaled SiGe channel devices show smallest time-dependent variability. Furthermore, we report comprehensive measurements of the impact of individual trapped charges on the entire FET ID-VG characteristic. Comparing with 3D atomistic device simulations, we identify several characteristic behaviors depending on the interplay between the location of the oxide defect and the underlying random dopant distribution.

Relation between breakdown mode and location in short-channel nMOSFETs and its impact on reliability specifications

A method to determine the breakdown position in short channel nMOSFETs is introduced. We find that soft breakdown occurs exclusively in the transistor channel, while the hardest circuit-killing breakdowns occur above the source and drain extension regions. Since these breakdowns make up only a small fraction of all breakdowns, a relaxation of the reliability specification is possible.

Analytical percolation model for predicting anomalous charge loss in flash memories

Data retention in flash memories is limited by anomalous charge loss. In this work, this phenomenon is modeled with a percolation concept. An analytical model is constructed that relates the charge-loss distribution of moving bits in flash memories with the geometric distribution of oxide traps. The oxide is characterized by a single parameter, the trap density. Combined with a trap-to-trap direct tunneling model, the physical parameters of the electron traps involved in the leakage mechanism are determined. Flash memory failure rate predictions for different oxide qualities, thicknesses and tunnel-oxide voltages are calculated.

Statistical Model for MOSFET Bias Temperature Instability Component Due to Charge Trapping

Bias temperature instability (BTI) is a serious reliability concern for MOS transistors. This paper covers theoretical analysis, Monte Carlo simulation, and experimental investigation of the charge trapping component of BTI. An analytical model for both stress and recovery phases of BTI is presented. Furthermore, the model properly describes device behavior under periodic switching, also called AC-BTI or cyclostationary operation. The model is based on microscopic device physics parameters, which are shown to cause statistical variation in transistor BTI behavior. It is shown that a universal logarithmic law describes the time dependence of charge trapping in both stress and recovery phases, and that the time dependence may be separated from the temperature and bias point dependence. Analytical equations for the statistical parameters are provided. The model is compared with experimental data and Monte Carlo simulation results.

Response of a single trap to AC negative Bias Temperature stress

We study the properties of a single gate oxide trap subjected to AC Bias Temperature Instability (BTI) stress conditions by means of Time Dependent Defect Spectroscopy. A theory for predicting the occupancy of a single trap after AC stress is developed based on first order kinetics and verified on experimental data. The developed theory can be used to develop circuit simulators and predict time dependent variability.

Layout impact on the performance of a locally strained PMOSFET

We present a study on the layout dependence of a SiGe S/D PMOSFET technology. While 65% increase in drive current is obtained for 45nm gate length transistors with large active areas, measurements and simulations show that this improvement may be seriously degraded when transistor dimensions, such as the source-drain length (L/sub s/d/) and the device width are further scaled. TDDB and NBTI measurements show that the oxide reliability is not degraded for this technology.