Jacopo Franco

Recent trends in bias temperature instability

Several trends occurring in the past few years in our understanding of bias temperature instability (BTI) are reviewed. Among the most important is the shift toward analyzing BTI relaxation with the tools originally developed for describing low-frequency noise. This includes the interpretation of the time, temperature, voltage, and duty cycle dependences. It is shown that a wealth of information about gate oxide defect properties can be obtained from deeply scaled devices and correctly modeled based on nonradiative multiphonon theory. It is then shown how detailed understanding of individual defect properties can allow interpreting the variability issues of future complementary metal-oxide semiconductor technologies. This is complemented by showing the most promising technological solutions for BTI.

Quantitative and predictive model of reading current variability in deeply scaled vertical poly-Si channel for 3D memories

3D vertical poly-Si channel SONOS devices are emerging as the most prominent alternative for the 10nm nonvolatile memory technology node and beyond (1-2) provided that a significant drive current IREAD is delivered at a fixed reading gate voltage VREAD. Recently, we showed the discrete drops observed in the transfer characteristic (ID vs. VG) of 3D transistors (Fig. 1) are linked to single electron trapping in the highly defective poly-Si channel (3). This effect, in addition to low poly-Si mobility, results in low drain current measured in poly-Si channel transistors (4). As an immediate consequence, a large drain current ID variability is observed in such deeply scaled devices (Fig. 1a). In order to develop a correct model predicting this ID variability, both i) the charging component and ii) the intrinsic gm-variability have to be separately characterized and physically understood to be afterwards correctly combined. The present abstract therefore aims at developing the methodology to predict the ID distribution at fixed reading gate voltage VREAD by physical understanding of both effects: electron trapping and transconductance variations.

Statistical Distribution of Defect Parameters

The statistics of bias temperature instability (BTI) is derived within the “defect-centric” paradigm of device degradation. This paradigm is first briefly reviewed, drawing on similarities between BTI and random telegraph noise (RTN). The impact of a single trap on FET threshold voltage V th is then shown to follow an exponential distribution with the expectation value η. The properties of η, such as its area and gate oxide thickness dependences, are discussed. The statistics of multiple defects is then developed, assuming (1) the single-trap exponential distribution and (2) a Poisson distribution of the number of traps in each device. The properties of the resulting time-dependent total ΔV th statistics and its moments are then treated. Finally, the combined time-dependent and time-zero statistics of the total threshold voltage V th is discussed, together with its properties and a brief example of its implications for circuit performance metrics.

Characterization and simulation methodology for time-dependent variability in advanced technologies

This paper describes the implications of Bias Temperature Instability (BTI) related time-dependent threshold voltage distributions on the performance and yield of devices and SRAM cells. We show that nFET and pFET time-dependent variability, in addition to the standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group (TEG) fabricated in an advanced technology. The statistical distributions encompassing both time-zero and time-dependent variability and their correlations are discussed. The assumption of Normally distributed threshold voltages, imposed by State-of-the-Art design approaches, is shown to induce inaccuracy which is readily solved by adopting our defect-centric statistical approach.

Channel Hot Carriers in SiGe and Ge pMOSFETs

In this chapter we discuss Channel Hot Carrier (CHC) degradation in high-mobility SiGe and Ge channel pMOSFETs. For Si technologies this degradation mode is of relevance for n-channel devices, while it is often neglected for p-channel devices whose reliability is typically limited by Negative Bias Temperature Instability (NBTI). However, for Ge-based p-channel, hot carrier effects are expected to worsen due to higher hole mobility and reduced channel bandgap enhancing impact ionization.

Defect-centric perspective of combined BTI and RTN time-dependent variability

This paper describes the implications of time-dependent threshold voltage variability, induced by Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), on the reliability and performance of advanced technology nodes. Investigation of time-dependent variability at the individual trap level, e.g. in production environments, is not feasible with approaches such as single device measurements developed in the academic literature. Nonetheless, nFET and pFET time-dependent variability, in addition to standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group. The statistical distributions encompassing both BTI and RTN variability and their correlations are discussed from a defect-centric perspective.

Characterization and modeling of charge trapping: From single defects to devices

Using time-dependent defect spectroscopy measurements on nanoscale MOSFETs, individual defects have been characterized in much greater detail than ever before. These studies have revealed the existence of metastable defect states which have a significant impact on the capture and emission time constants. For example, these defect states explain the large emission time constants observed in bias temperature measurements as well as the switching behavior of defects sensitive to gate bias changes towards accumulation. By carefully analyzing the properties of the defects contributing to random telegraph noise and the recoverable component of the bias temperature instability, it could be confirmed that both phenomena are due to the same type of defect. The most fundamental property of these defects is that their time constants are widely distributed, leading to the ubiquitous time and frequency dependence. By transferring this knowledge to large area devices, noise as well as the response to bias temperature stress and recovery can be understood in great detail.

NBTI in (Si)Ge Channel Devices

This chapter focuses on the negative bias temperature instability (NBTI) of the novel Ge-based high-mobility channel pMOS technology, with Si passivation scheme and SiO2/HfO2 dielectric stack. We observe that this technology offers a remarkable reliability improvement. In particular, a significantly reduced NBTI is obtained by optimizing the gate stack with a high Ge fraction in the channel, a sufficiently thick channel quantum well, and a Si passivation layer of reduced thickness. By means of such optimization, sufficiently reliable ultrathin EOT SiGe pMOSFETs with a 10-year lifetime at operating conditions are demonstrated in both gate-first and gate-last process flows. Furthermore, the reliability improvement is observed to be process independent and architecture independent, proving to be an intrinsic property of the studied MOS system consisting of a Ge-based channel and a SiO2/HfO2 dielectric stack.

Statistical assessment of the full V G /V D degradation space using dedicated device arrays

Variability of as-fabricated (i.e., time-zero) parameters of modern VLSI devices has been considered in circuit design tools for some time. Also work on parametrizing time-dependent variability has been presented, with associated degradation mechanisms Random Telegraph Noise (RTN) and Bias Temperature Instabilities (BTI). Statistics on other FET degradation modes such as Hot Carrier Degradation (HCD) and Off-State-Stress (OSS) are, however, sparse. In this work, we design and measure a fabricated test array allowing us to capture degradation statistics, obtain the mean and the variance of multiple device degradation metrics (ΔVTH, Δgm,…) for an arbitrary (VG, VD) combination and show that time-dependent variability induced by channel HCD in deeply scaled devices is much more severe than (positive) BTI-induced variability.

Beyond-Si materials and devices for more Moore and more than Moore applications

In this work, we will review the current progress in high mobility devices and new device architectures. With main focus on (Si)Ge for pMOS and In(Ga)As for nMOS, the benefits and challenges of integrating these materials on a Si platform will be discussed. Next to that, the advantages of tunnel FETs, vertical logic and in general heterogeneous integration will be highlighted.