Ph. Roussel

Atomistic approach to variability of bias-temperature instability in circuit simulations

A blueprint for an atomistic approach to introducing time-dependent variability into a circuit simulator in a realistic manner is demonstrated. The approach is based on previously proven physics of stochastic properties of individual gate oxide defects and their impact on FET operation. The proposed framework is capable of following defects with widely distributed time scales (from fast to quasi-permanent), thus seamlessly integrating random telegraph noise (RTN) effects with bias temperature instability (BTI). The use of industry-standard circuit simulation tools allows for studying realistic workloads and the interplay of degradation of multiple FETs.

Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs

We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different technologies, based on which we propose a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on the electrical characteristic of deeply scaled transistors. Among the considered technologies, nanoscaled SiGe channel devices show smallest time-dependent variability. Furthermore, we report comprehensive measurements of the impact of individual trapped charges on the entire FET ID-VG characteristic. Comparing with 3D atomistic device simulations, we identify several characteristic behaviors depending on the interplay between the location of the oxide defect and the underlying random dopant distribution.

Degradation and breakdown of 0.9 nm EOT SiO/sub 2/ ALD HfO/sub 2/metal gate stacks under positive constant voltage stress

By means of leakage current measurements, charge pumping and TDDB analysis, we construct a consistent model for the degradation and breakdown of 0.9 nm EOT atomic layer deposited (ALD) HfO2. During degradation, traps and two-trap clusters are formed in the HfO 2 giving rise to considerable SILC. The two-trap clusters subsequently wear out, finally leading to an abrupt hard breakdown. We demonstrate that 0.9 nm EOT ALD HfO2 is intrinsically reliable under constant voltage stress if hard breakdown is used as a failure criterion

Response of a single trap to AC negative Bias Temperature stress

We study the properties of a single gate oxide trap subjected to AC Bias Temperature Instability (BTI) stress conditions by means of Time Dependent Defect Spectroscopy. A theory for predicting the occupancy of a single trap after AC stress is developed based on first order kinetics and verified on experimental data. The developed theory can be used to develop circuit simulators and predict time dependent variability.

Defect-based methodology for workload-dependent circuit lifetime projections - Application to SRAM

Despite a number of recent advances made in understanding bias temperature instability (BTI), there is still no simple simulation methodology available which can capture the impact of BTI degradation on deeply scaled transistors, while incorporating the widely distributed defect parameters. We present a physics-based defect-controlled methodology for projecting defect property distributions into circuit lifetime and performance distributions. This methodology allows evaluating the entire population of traps (from fast to slow recoverable and permanent traps), which results in faster simulation and proper extrapolation towards long operating lifetimes.

Observation of hot-carrier-induced nFET gate-oxide breakdown in dynamically stressed CMOS circuits

Subjecting a ring oscillator circuit with short-channel thin-oxide FETs to dynamic stress results in the majority of nFET and pFET drain-side gate-oxide breakdowns. The enhancement in the drain-side breakdowns, which are potentially the most detrimental to circuit operation, is shown to be induced in nFETs by channel hot carriers.

Abrupt breakdown in dielectric/metal gate stacks: a potential reliability limitation?

In downscaled poly-Si gate MOSFET devices reliability margin is gained by progressive wearout. When the poly-Si gate is replaced with a metal gate, the slow wearout phase observed in ultrathin SiON and HfSiON dielectrics with poly-Si gate disappears, and with it, the reliability margin. We demonstrate for several combinations of dielectric and gate materials that the large abrupt current increase (/spl Delta/I) as compared to poly-Si is not likely due to process issues, but is an intrinsic property of the dielectric/metal gate stack. The occurrence of large /spl Delta/I is a potential limitation for the reliability of metal gate devices.

Correlation of single trapping and detrapping effects in drain and gate currents of nanoscaled nFETs and pFETs

The correlation of discrete gate and drain current fluctuations is revealed in nanoscaled SiON pFETs and nFETs, demonstrating that discrete trapping and detrapping events in the same single states are responsible of both ID and IG random telegraph noise (RTN). The high and low gate current IG-RTN levels are independent of temperature but the switching rates thermally activated indicating that the trapping and detrapping events are consistent with nonradiative multiphonon theory.

The relevance of deeply-scaled FET threshold voltage shifts for operation lifetimes

In nm-sized FET devices with just a few gate oxide defects, the typically measured threshold voltage shifts are not obviously correlated with the device behavior at high gate bias. The largest shifts observed at the threshold voltage after the capture of a single carrier are reduced at higher gate biases. This degradation-mitigating effect is further shown to be amplified at lower channel doping. The understanding gained from 3D numerical simulations is captured in a simple analytic description of a single trapped-charge impact on the FET characteristics in the entire gate bias range. Potential use is illustrated in an improved lifetime projection and in circuit simulations of time-dependent variability.

Spectroscopic. ellipsometry for depth profiling of ion implanted materials

Abstract The application of Spectroscopic ellipsometry (SE) to obtain accurate depth profiles of ion-implanted silicon substrates is discussed. Details on the interpretation of SE spectra are given, explaining why such a complex analysis is possible. The power of SE to nondestructively obtain depth profiles of ion implantation damage is illustrated for hydrogen-implanted silicon and on low-dose implanted SIMOX (Separation by IMplanted OXygen) material. The obtained SE results are verified by cross-sectional transmission electron microscopy and by other analytical techniques.