Pieter Weckx

Defect-based methodology for workload-dependent circuit lifetime projections - Application to SRAM

Despite a number of recent advances made in understanding bias temperature instability (BTI), there is still no simple simulation methodology available which can capture the impact of BTI degradation on deeply scaled transistors, while incorporating the widely distributed defect parameters. We present a physics-based defect-controlled methodology for projecting defect property distributions into circuit lifetime and performance distributions. This methodology allows evaluating the entire population of traps (from fast to slow recoverable and permanent traps), which results in faster simulation and proper extrapolation towards long operating lifetimes.

Implications of BTI-Induced Time-Dependent Statistics on Yield Estimation of Digital Circuits

This paper describes the implications of bias temperature instability (BTI)-induced time-dependent threshold voltage distributions on the performance and yield estimation of digital circuits. The statistical distributions encompassing both time-zero and time-dependent variability and their correlations are discussed. The impact of using normally distributed threshold voltages, imposed by state-of-the-art design approaches, is contrasted with our defect-centric approach. Extensive Monte Carlo simulation results are shown for static random access memory cell and ring oscillator structures.

Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates

In deeply scaled CMOS technology, time-dependent degradation mechanisms (TDDMs), such as Bias Temperature Instability (BTI), have threatened the transistor performance, hence the overall circuit/system reliability. Two well-known attempts to model BTI mechanism are the reaction-diffusion (R-D) model and the Atomistic trap-based model. This paper presents a thorough comparative analysis of the two models at the gate-level in order to explore when their predictions are the same and when not. The comparison is done by evaluating degradation trends in a set of CMOS logic gates (e.g., INV, NAND, NOR, etc.) while considering seven attributes: 1) gate type, 2) gate drive strength, 3) input frequency, 4) duty factor, 5) non-periodicity, 6) instant degradation versus long-term aging, and 7) simulation CPU time and memory usage. The simulation results show that two models are in consistency in terms of the gate degradation trends w.r.t. the first four attributes (gate type, input frequency, etc.). For the rest of the attributes, the workload-dependent solution of the Atomistic trap-based model is superior from the point of non-periodicity and instant degradation, while the R-D model gets advantageous in case of long-term aging, and simulation CPU time and memory usage due to its lite AC periodic and duty factor dependent solution.

Atomistic Pseudo-Transient BTI Simulation With Inherent Workload Memory

Bias Temperature Instability (BTI) is a major concern for the reliability of decameter to nanometer devices. Older modeling approaches fail to capture time-dependent device variability or maintain a crude view of the devices stress. Previously, a two-state atomistic model has been introduced, which is based on gate stack defect kinetics. Its complexity has been preventing seamless integration in simulations of large device inventories over typical system lifetimes. In this paper, we present an approach that alleviates this complexity. We introduce a novel signal representation for the gate stress. Using this format, atomistic BTI simulations require less model iterations while exhibiting minimum accuracy degradation. We also enable full temperature and voltage supply dependency since these attributes are far from constant in modern integrated systems. The proposed simulation methodology retains both the atomistic property and the workload memory that remain major differentiators of defect-based BTI simulation, in comparison to state-of-the-art approaches.

Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology

Here we show that nFET and pFET time-dependent variability, in addition to the standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group (TEG) fabricated in an advanced High-k/Metal Gate (HK/MG) technology, thus allowing us to fully characterize the underlying technology. BTI is shown to follow a bimodal defect-centric behavior, for NBTI related to Interface Layer (IL)(SiO2) and HK trapping and for PBTI related to HK and IL/HK interface trapping. Moreover for the first time, an analytical description of the bimodal total ΔVTH shift is derived, as a special case of the generalized defect-centric distribution, which we derive in this work to accurately describe the tail of the distribution.

Maximizing reliable performance of advanced CMOS circuits—A case study

We consider in detail the aspects of maximizing application performance while maintaining its sufficient reliability on the specific case of serially connected nFETs. Serially connected nFETs used in some digital CMOS applications, such as SRAM decoder circuits, and dynamic logic, are vulnerable to Positive Bias Temperature Instability (PBTI). Here we discuss the impact of PBTI frequency and workload on high-k/metal gate nFETs in terms of Capture and Emission Time (CET) maps and quantitatively explain the degradation of our test circuit. This constitutes one of the first validations of the CET map-based methodology on a real silicon circuit. From individual trapping events in deeply scaled nFETs we then project PBTI distributions at 10 years. We further show that at increased supply voltage the serially connected nFET speed degradation is outweighed by signal transfer speedup, resulting in a net performance improvement. Finally, we discuss other degradation mechanisms and conclude the reliability in the studied case will be limited by hard gate oxide breakdown.

Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology

Reliability of advanced deeply scaled CMOS technologies is being threatened by time-dependent degradation mechanisms such as Negative Bias Temperature Instability (NBTI) phenomenon that cause workload-dependent shifts on a transistors threshold voltage (Vth), and performance during its lifetime. In this study, NBTI related performance degradation of datapath logic subblocks (i.e. adder, multiplier, shifter, mux-demux) are investigated in relation to workload dependency, and architectural topology at 10nm FinFET technology. A workload-dependent, NBTI aging-aware digital design flow was developed within the industry standard EDA tool chain. NBTI model is based on the measured Capture and Emission Time (CET) maps, and scaled to 10nm node. Static Timing Analysis (STA) is performed to evaluate the performance degradation at 3σ corner. Results on datapath subblocks under NBTI aging after 3 years show a performance loss up to 16.7%. NBTI aging results in the replacement of the time-zero critical path by a non-critical path during a circuits lifetime, and it can be significantly high as 91%. Finally, the correlation between aging sensitivity to workload variations, and architectural parameters are shown, and it can vary 12×, and 9×, respectively.

Non-Monte-Carlo methodology for high-sigma simulations of circuits under workload-dependent BTI degradation—Application to 6T SRAM

Recent advances in understanding Bias Temperature Instability (BTI) in terms of individual gate oxide defects has created a paradigm shift towards describing degradation in terms of time-dependent variability. This added time dimension to the variability analysis has proven to be a considerable design challenge. Moreover, the non-normally distributed ΔVTH shifts create compatibility issues with the current SotA statistical assessments techniques for evaluating high sigma yield of SRAM cells. Here we present a novel Non-Monte-Carlo numerical simulation methodology capable of evaluating circuit performance under workload-dependent BTI degradation.

Origins and implications of increased channel hot carrier variability in nFinFETs

Channel hot carrier (CHC) stress is observed to result in higher variability of degradation in deeply-scaled nFinFETs than bias temperature instability (BTI) stress. Potential sources of this increased variation are discussed and the intrinsic time-dependent variability component is extracted using a novel methodology based on matched pairs. It is concluded that in deeply-scaled devices, CHC-induced time-dependent distributions will be bimodal, pertaining to bulk charging and to interface defect generation, respectively. The latter, high-impact mode will control circuit failure fractions at high percentiles.

Scaling of BTI reliability in presence of time-zero variability

In this paper, we first outline the impact of Bias Temperature Instability (BTI) on the transistor threshold voltage as a function of time and the gate oxide field. Subsequently, the correlation between time-zero and time-dependent variability is described. A combined distribution encompassing both contributions with their relative weights is derived. Finally, circuit-level insights on the BTI impact are given based on case study simulations of Ring Oscillators (ROs) at commercial-grade 28nm planar and research-grade 14, 10, 7nm FinFET technology nodes for several FET channel materials (e.g. Si, SiGe, Ge, InGaAs).