B. Spangenberg

Residual stress in Si nanocrystals embedded in a SiO2 matrix

Multiple quantum wells consisting of alternating Si and SiO2 layers were studied by means of Raman scattering. The structures were fabricated by the remote plasma enhanced chemical vapor deposition of amorphous Si and SiO2 layers on quartz substrate. The structures were subjected to a rapid thermal annealing procedure for Si crystallization. The obtained results suggest that the Si layers consist of nanocrystals embedded in an amorphous Si phase. It was found that the silicon nanocrystals inside 2nm thin layers are under high residual compressive stress. Moreover, the metastable Si III phase was detected in these samples supporting the presence of large compressive stresses in the structures. The compressive stress could be relaxed upon local laser annealing.

Lateral Si/SiO2 quantum well solar cells

The photovoltaic properties of Si∕SiO2 multiple quantum wells (QWs) embedded in lateral Schottky contacts are investigated. The QWs were fabricated by remote plasma enhanced chemical vapor deposition. By subsequent rapid thermal annealing, the two-dimensional Si layers are partially recrystallized, which gives rise to distinct quantum confinement effects. Although the current extraction along the quantum layers is hampered by the incomplete recrystallization, the data collected define the route to optimized Si based QW solar cells.

Concept of floating-dot memory transistors on silicon-on-insulator substrate

Abstract Two different concepts of floating-dot memories are compared. In addition to the well known concept of nanodots in SiO 2 -environments a novel architecture where oxidized floating nanodots are embedded directly in a gate material is investigated.

Influence of channel width on n - and p -type nano-wire-MOSFETs on silicon on insulator substrate

The fabrication and characterization of nanoscale n- and p-type multi-wire metal-oxide semiconductor field effect transistors (MOSFETs) with a triple gate stracture on silicon-on-insulator material (SOI) is described in this paper. Experimental results are compared to simulation with special emphasis on the influence of channel width on the subthreshold behavior. Experiment and simulation show that the threshold voltage depends strongly on the wire width at dimensions below 100 nm. It is further shown that the transition from partial to full channel depletion is dependent on channel geometry. Finally, an increased on-current per chip area is demonstrated for triple-gate SOI MOSFETs compared to planar SOI devices.

Properties of evaporated titanium thin films and their possible application in single electron devices

Abstract The influence of the deposition rate of titanium thin films on their microscopic structure has been investigated by transmission electron microscopy, X-ray diffraction analyses and atomic force microscopy. Furthermore, the resistivity of the films has been characterized by van der Pauw measurements in a temperature range of 5–300 K. Titanium films with a thickness of 10 nm evaporated with a rate of 1 A/s showed the typical and well known temperature dependency of the resistivity (i.e. decreasing resistivity with falling temperature). In contrast, the resistivity of thin films deposited with a rate of 0.2 A/s rises with decreasing temperature. Additionally, the resistivity of the films evaporated with the lower rate rises significantly when reducing their film thickness down to 3 nm. Due to this increase of the resistivity we are able to present an alternative and relatively simple approach for the fabrication of single electron transistors (SETs). The presented SET design is based on the evaporated thin titanium films with a deposition rate of 0.2 A/s onto well defined trenches previously etched into a dielectric layer of thermally grown silicon dioxide. The tunnel junctions originate from a local increase of the resistance of the metallic wire at the edges of the trenches. The devices fabricated in this manner with lateral dimensions in the 50–100 nm range show clear SET features at an operating temperature of up to 77 K. Additionally, the influence of background charges on the Coulomb oscillations in this devices are demonstrated and discussed in comparison with simulated data.

Optimization of YBa2Cu3O7−δ submicrometer structure fabrication

We present a study of the sputter etching step in the fabrication sequence of YBa2Cu3O7−δ submicrometer structures down to 200 nm linewidth. We identify oxygen effusion as the main reason for process‐induced degradation of superconductivity. Oxygen reloading by plasma oxidation after pattern transfer efficiently recovers both the transition temperature Tc and the critical current density jc of the YBa2Cu3O7−δ submicrometer structures. Liquid‐nitrogen cooling of the substrate is shown to efficiently suppress oxygen effusion during sputter etching. Critical current densities above 106 A/cm2 at 77 K are obtained for 0.75 μm wide and 10 μm long bridges.

Subthreshold characteristics of p-type triple-gate MOSFETs

The fabrication and characterization of triple-gate p-type metal-oxide semiconductor field effect transistors (p-MOSFETs) on SOI material with multiple channels is described. To demonstrate the beneficial effects of the triple-gate structure on scaling, the output and transfer characteristics of 70 nm printed gate length pMOSFETs with 22 nm MESA width are presented. The geometrical influence of triple-gate MESA width on subthreshold behavior is investigated in short- and long channel devices. The temperature dependence of subthreshold characteristics is discussed.

Improved charge transport through Si based multiple quantum wells with substoichiometric SiOx barrier layers

The vertical charge transport through Si/SiOx multiple quantum wells (QWs) is investigated. Upon thermal annealing, segregation of excess Si from the SiOx layers leads to the formation of highly conductive pathways between Si grains from adjacent QWs separated by ultrathin silicon oxide barriers with barrier heights of 0.53–0.65 eV. Compared to stoichiometric Si/SiO2 layer stacks, conductivity is increased by up to ten orders of magnitude, which opens the way to an efficient charge carrier extraction in photovoltaic systems with distinct quantum confinement.

Resonant and phonon-assisted tunneling transport through silicon quantum dots embedded in SiO2

Charge transport through SiO2∕Si∕SiO2 double-barrier structures (DBSs) and SiO2 single-barrier structures is investigated by low temperature I-V measurements. Resonant tunneling signatures accompanied by a negative differential conductance are observed if silicon quantum dots (Si QDs) are embedded in the amorphous SiO2 matrix. The I-V characteristics are correlated with the morphology of Si QDs extracted from transmission electron microscopy and photoluminescence. Evidence for phonon-assisted tunneling at low voltages has been found in the DBSs. These results show the potential but also the limitation for charge extraction from Si QDs embedded in SiO2.

Monolithic bidirectional switch (MBS) - a novel MOS-based power device

A novel MOS-based power device, the monolithic bidirectional switch (MBS), is investigated in this work. An analytical model is used to explain basic device operating principles. A self-aligned fabrication process of lateral MBS devices with Schottky contacts and local oxidation of silicon technique (LOCOS) is described. Experimental results are compared with the analytical model to analyze the influence of device parasitics. Bidirectional switching and an on/off-current ratio of more than 100 is demonstrated for MBS devices for the first time.