Karl Hofmann

An Effective Switching Current Methodology to Predict the Performance of Complex Digital Circuits

A new methodology to assess dynamic circuit performance using basic device currents is presented. In contrast to existing effective drive current calculation considering inverters only, our approach provides precise circuit delays of product-relevant NAND and NOR logic gates over a wide range of supply voltages. The relevance of currents in the linear regime for circuit performance in sub-65 nm CMOS technologies is demonstrated also experimentally by a 65% performance boost in complex multi-gate FET circuits.

Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS

Spin-torque-transfer (STT) MRAM is a promising candidate for embedded non-volatile memory in next generation microcontrollers, because of superior endurance, low process costs and logic supply voltage operation. Two major drawbacks of STT-MRAM technology are the small read window because of the low tunnel magnetic resistance (TMR) ratio, and the low read current due to read disturb, which is proportional to the bitline (BL) voltage [1].

A 65nm test structure for the analysis of NBTI induced statistical variation in SRAM transistors

We present the results of a test structure that allows to measure the variation of SRAM p-MOS and n-MOS transistors in a dense environment and to apply Negative Bias Temperature Instability (NBTI) stress on the p-MOS transistors. The threshold voltage (Vth) and drain current (Id) distributions of p-MOS SRAM transistors pre and post NBTI Stress are measured and analyzed. The probability density functions (PDF) of both transistor parameters Vth and Id follow a Gaussian distribution pre and post NBTI stress, but the difference in the transistor parameters of an individual device is not Gaussian distributed. The standard deviation in the difference of Vth is about 50% of the mean for the small SRAM p-MOS transistor. The impact of the additional variation induced by NBTI stress is shown for the Static Noise Margin of a 6-T SRAM cell.

Highly accurate product-level aging monitoring in 40nm CMOS

A product-level aging monitor replicating a 40nm CMOS ARM1176 critical path is presented. The monitor enables a separation of the dominating negative bias instability (NBTI) stress, including speed recovery, and the switching-activity dependent hot carrier stress (HCS). The comprehensive analysis comprises transistor and circuit level measurements as well as simulations. The monitor results demonstrate that the overall circuit performance degradation, even at high frequencies and large switching activities, is 2% for wireless-typical operating conditions.

The impact of recovery on BTI reliability assessments

BTI is shown to be the most important device degradation mechanism for combinational logic. Significant benefits regarding lifetime predictions and the total effort in measurement time can be expected from measurements minimizing recovery by a short measuring delay or/and assessments being done with AC stress for applications ensuring AC operation only.

Impact of fast-recovering NBTI degradation on stability of large-scale SRAM arrays

This paper presents stability analysis of large-scale SRAM arrays directly after terminating NBTI stress. While the impact of static NBTI is well examined for cells and arrays, the fast-recovering component was not yet measured on SRAM arrays. The novel method presented here analyzes the flipping of cells directly after the supply voltage was lowered to a specific value where the structure is most sensitive for NBTI induced cell flips. Thus, read margin criterion is used to characterize the decreasing cell stability due to NBTI degradation with a resolution down to 1 ms. Applying this method, the impact of static and dynamic NBTI is measured in a 65 nm low power CMOS technology. Between 1 ms and 10.000 s after stress, the NBTI induced number of cell flips decreases by almost one half.

Fast stability analysis of large-scale SRAM arrays and the impact of NBTI degradation

This paper presents Read Margin analysis for large SRAM arrays with a fast test method that even can be realized in dual-VDD product chips. Classical Static Noise Margin (SNM) is mostly suitable for single-cell simulation. Read Margin (RM) measurement allows analysis of large arrays and correlates to SNM, but requires a dedicated teststructure and long measurement time. The presented method analyzes the flipping of cells over varying supply voltage. The stability of large arrays can be characterized in read as well as in hold state depending on the state of the access transistors. Applying this method, the impact of Negative Bias Temperature Instability (NBTI) is demonstrated on both Read and Hold Margin in a 65 nm low power technology.

Comprehensive statistical investigation of STT-MRAM thermal stability

The thermal stability Δ is a key parameter of the MRAM technology. It determines the current induced switching behavior as well as the reliability performance of e.g. data retention and read-disturb. Therefore a highly accurate assessment of Δ is mandatory for a successful MRAM technology development. In this paper we present a verification methodology based on the statistical data of a 8Mb test vehicle revealing a wide Δ distribution of ~17%.

A voltage scaling model for performance evaluation in digital CMOS circuits

We present an easy to use method to extrapolate digital circuit performance and power from nominal to worst-case operating conditions. It allows the circuit designer to explore the design space over a continuous rage of voltages and temperatures and for different process conditions. Voltage scaling is identified as a key challenge for the 22nm technology node.