M. Baus

A Graphene Field-Effect Device

In this letter, a top-gated field-effect device (FED) manufactured from monolayer graphene is investigated. Except for graphene deposition, a conventional top-down CMOS-compatible process flow is applied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from the top-gated Graphene-FEDs. The extracted values exceed the universal mobility of silicon and silicon-on-insulator MOSFETs

Nonvolatile Switching in Graphene Field-Effect Devices

The absence of a band gap in graphene restricts its straightforward application as a channel material in field-effect transistors. In this letter, we report on a new approach to engineer a band gap in graphene field-effect devices (FEDs) by controlled structural modification of the graphene channel itself. The conductance in the FEDs is switched between a conductive ldquoon-staterdquo and an insulating ldquooff-staterdquo with more than six orders of magnitude difference in conductance. Above a critical value of an electric field applied to the FED gate under certain environmental conditions, a chemical modification takes place to form insulating graphene derivatives. The effect can be reversed by electrical fields of opposite polarity or short current pulses to recover the initial state. These reversible switches could potentially be applied to nonvolatile memories and novel neuromorphic processing concepts.

Synthesis of Graphene on Silicon Dioxide by a Solid Carbon Source

We report on a method for the fabrication of graphene on a silicon dioxide substrate by solid-state dissolution of an overlying stack of a silicon carbide and a nickel thin film. The carbon dissolves in the nickel by rapid thermal annealing. Upon cooling, the carbon segregates to the nickel surface forming a graphene layer over the entire nickel surface. By wet etching of the nickel layer, the graphene layer was allowed to settle on the original substrate. Scanning tunneling microscopy (STM) as well as Raman spectroscopy has been performed for characterization of the layers. Further insight into the morphology of the layers has been gained by Raman mapping indicating micrometer-size graphene grains. Devices for electrical measurement have been manufactured exhibiting a modulation of the transfer current by backgate electric fields. The presented approach allows for mass fabrication of polycrystalline graphene without transfer steps while using only CMOS compatible process steps.

Concept of floating-dot memory transistors on silicon-on-insulator substrate

Abstract Two different concepts of floating-dot memories are compared. In addition to the well known concept of nanodots in SiO 2 -environments a novel architecture where oxidized floating nanodots are embedded directly in a gate material is investigated.

Influence of channel width on n - and p -type nano-wire-MOSFETs on silicon on insulator substrate

The fabrication and characterization of nanoscale n- and p-type multi-wire metal-oxide semiconductor field effect transistors (MOSFETs) with a triple gate stracture on silicon-on-insulator material (SOI) is described in this paper. Experimental results are compared to simulation with special emphasis on the influence of channel width on the subthreshold behavior. Experiment and simulation show that the threshold voltage depends strongly on the wire width at dimensions below 100 nm. It is further shown that the transition from partial to full channel depletion is dependent on channel geometry. Finally, an increased on-current per chip area is demonstrated for triple-gate SOI MOSFETs compared to planar SOI devices.

Subthreshold characteristics of p-type triple-gate MOSFETs

The fabrication and characterization of triple-gate p-type metal-oxide semiconductor field effect transistors (p-MOSFETs) on SOI material with multiple channels is described. To demonstrate the beneficial effects of the triple-gate structure on scaling, the output and transfer characteristics of 70 nm printed gate length pMOSFETs with 22 nm MESA width are presented. The geometrical influence of triple-gate MESA width on subthreshold behavior is investigated in short- and long channel devices. The temperature dependence of subthreshold characteristics is discussed.

Monolithic bidirectional switch (MBS) - a novel MOS-based power device

A novel MOS-based power device, the monolithic bidirectional switch (MBS), is investigated in this work. An analytical model is used to explain basic device operating principles. A self-aligned fabrication process of lateral MBS devices with Schottky contacts and local oxidation of silicon technique (LOCOS) is described. Experimental results are compared with the analytical model to analyze the influence of device parasitics. Bidirectional switching and an on/off-current ratio of more than 100 is demonstrated for MBS devices for the first time.

Device architectures based on graphene channels

Graphene is a possible candidate for advanced channel materials in future field effect transistors. This presentation gives a brief overview about recent experimental results in the field of graphene transistors for future electronic applications.

Floating-dot Memory Transistors on SOI Substrate

Non-volatile memories have become an indispensable part of today’s digital data processing. The quickly growing mobile electronics market especially fuels the demand for these devices. The presented floating-dot memory concept discloses a related and CMOS-compatible alternative with enhanced write/erase endurance compared to FLASH while not demanding severe changes of the manufacturing process at the same time. Here, the charge-storing silicon nano-dots are deposited by a self-organized LPCVD technique. The introduced concept is based on advanced SOI substrates, which exhibit fabrication as well as device advantages and offer higher scaling potential than conventional bulk silicon substrates. The electrical data of the presented examination devices prove the suitability of the floatingdot memory concept and pave the way for enhanced non-volatile memory devices.