Joung-yeal Kim

CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction

A CMOS charge pump based on a transfer blocking technique and a modified precharge scheme is proposed for avoiding reversion loss and relaxing the timing restrictions imposed on input clocks. Comparison results in an 80-nm CMOS process indicate that, with no loading current, the output voltage of the proposed charge pump reaches almost 98% of the ideal boosting level with switching ripple reduced by up to 97%. They also indicate that output voltage deviations due to temperature and process variations are reduced by 24%-98% and 81%-95%, respectively.

NGN architecture for IPTV service without effect on conversational services

ITU-T FGNGN plans to complete NGN Release 1 scope at this year. It, thus, is the time to start NGN Release 2 scope, such as streaming service including IPTV, VoD, etc. This paper proposes new NGN architecture for IPTV services to progress NGN Release 2

CMOS cross-coupled charge pump with improved latch-up immunity

In this paper, a novel CMOS charge pump with substantially improved immunity to latch-up is presented. By utilizing a dedicated bulk pumping and blocking (DBPB) technique, the proposed charge pump achieves greatly reduced forward voltage of source/drain-substrate junction of transistors, resulting in decreased charge loss and increased latch-up immunity. Comparison results indicated that the maximum bulk forward voltage of the proposed charge pump was less than 0.05V (88% improvement) for zero output current during power-up, and less than 0.12V (88% improvement) regardless of the amount of output current during ordinary pumping operation.

CMOS Charge Pump With No Reversion Loss and Enhanced Drivability

A CMOS charge pump adopting dual charge transfer switches and a transfer blocking technique is presented. Using these techniques, the proposed charge pump eliminates reversion loss and improves driving capability. A test chip is designed in a 46-nm CMOS process, whose evaluation results show that, with no loading current, the proposed CMOS charge pump achieves 9.1% improvement of voltage conversion ratio. They also show that the proposed charge pump provides up to 132% improvement on current driving capability, as compared with the conventional CMOS charge pumps.

Novel Low-Voltage Small-Area I/O Buffer for Mixed-Voltage Application

Novel mixed-voltage I/O buffer with fast low-voltage operation and small-area realization is proposed. The I/O buffer provides reduced latency at low supply voltages by eliminating the voltage swing degradation at timing-critical nets. The buffer also provides smaller layout area by avoiding dedicated bulky circuits like dynamic gate-bias circuit (DGBC) and hot-carrier prevention circuit (HCPC). Evaluation results in 130-nm CMOS process indicated that the proposed mixed-voltage I/O buffer achieves up to 52% reduction on latency and up to 39% reduction on layout area as compared to conventional mixed-voltage I/O buffers.

New low-voltage small-area mixed-voltage I/O buffer

A new mixed-voltage I/O buffer having the characteristics of low-voltage operation and small-area realization is proposed. The proposed I/O buffer provides significantly reduced latency at low supply voltages by eliminating the voltage swing degradation at timing-critical nets. The buffer also provides smaller layout area by avoiding the use of dedicated extra circuits like dynamic gate-bias circuit (DGBC) and hot-carrier prevention circuits (HCPC) to cope with hot-carrier-induced gate-oxide reliability issue. Comparison results in an 80-nm CMOS process indicate that the proposed mixed-voltage I/O buffer achieves 73% reduction on buffer latency, 23% reduction on operating voltage, and 31% reduction on layout area as compared to conventional I/O buffers.