Bao G. Truong

High-speed interconnect and packaging design of the IBM System z9 processor cage

This paper describes the system packaging and technologies of the IBM System z9TM enterprise-class server. The central electronic complex of the system consists of four nodes, each housing a multichip module (MCM) with 16 chips consuming up to 1,200 W. The z9TM server doubles the multiprocessor performance of the System z990 by increasing the central processing unit (CPU) configuration and using an internally developed elastic interface to increase interconnect speed on all high-speed buses. In contrast to all previous zSeries® designs, which were running at half of the processor speed, the packaging interconnects on the multichip module run at the same speed as the processor (1.72 GHz). High frequencies and massively parallel connectivity lead to a raw packaging bandwidth of up to 1,764 GB/s between processors and cache within a single frame for a fully configured four-node z9 system.

IBM Power5 bus designs for on- and off-module connections

This work overviews the interface choices made for the 1:1 on-module buses and the 2:1 off-module buses. Custom circuits used, data recovery methods, signal integrity design and the system verification using register based diagnostics and eye margin mapping. The hardware based verification methods that heavily rely on the interface register based diagnostics and margin mapping are explained.