Roger D. Weekly

An advanced multichip module (MCM) for high-performance UNIX servers

In 2001, IBM delivered to the marketplace a high-performance UNIX?®-class eServer based on a four-chip multichip module (MCM) code named Regatta. This MCM supports four POWER4 chips, each with 170 million transistors, which utilize the IBM advanced copper back-end interconnect technology. Each chip is attached to the MCM through 7018 flip-chip solder connections. The MCM, fabricated using the IBM high-performance glass-ceramic technology, features 1.7 million internal copper vias and high-density top-surface contact pad arrays with 100-?µm pads on 200-?µm centers. Interconnections between chips on the MCM and interconnections to the board for power distribution and MCM-to-MCM communication are provided by 190 meters of co-sintered copper wiring. Additionally, the 5100 off-module connections on the bottom side of the MCM are fabricated at a 1-mm pitch and connected to the board through the use of a novel land grid array technology, thus enabling a compact 85-mm ?? 85-mm module footprint that enables 8- to 32-way systems with processors operating at 1.1 GHz or 1.3 GHz. The MCM also incorporates advanced thermal solutions that enable 156 W of cooling per chip. This paper presents a detailed overview of the fabrication, assembly, testing, and reliability qualification of this advanced MCM technology.

Optimum design of power distribution system via clock modulation

This paper presents a method for extracting current excitations, which a microprocessor (/spl mu/P) can present to its power distribution system (PDS) as a function of frequency. The method uses a clock modulation technique to measure the impedance seen by the uP.

Minimizing crosstalk noise in vias or pins by optimizing signal assignment in a high-speed differential bus

Vias in packages and boards, land-grid-array pins, and connector pins introduce significant crosstalk in high-speed differential buses. There are many possible differential signal assignments in those areas that have very different electrical performance. This paper proposes and demonstrates an efficient method to find a large number of possible assignments and assess them to obtain an optimal assignment with the best performance.

Signal propagation over perforated reference planes

Voids on reference planes are commonly seen in organic chip packages and printed circuit boards. In this paper, the effects of these voids on the signal integrity of a high-density data bus will be studied. A generic FCPBGA chip package is used to illustrate the signal integrity concerns and perform sensitivity analysis on the key mechanisms including void size, adjacent plane interactions, and adjacent signal line interactions. The results show that proper design can mitigate the signal integrity impact of reference plane voids.

Power distribution analysis for IBM eServer system integration optimization

Server system design is strongly influenced by power delivery aspects. Multiple requirements and limitations must be taken into consideration. This requires an appropriate DC analysis workflow. This contribution outlines a DC strategy used for IBM eServer design. The strategy is divided into two parts, PrePD and PostPD. PrePD type of analysis is used for system high-level design and optimization including parts selection, number of board layers, module sizing and placement on board, interface pin pattern optimization for both module to board and board to backplane. PostPD analysis is used for first level packaging design optimization and verification. The combination of PrePD and PostPD analysis serves as an efficient and useful tool, shown by the examples of various applications, for server power delivery system design.

Methodology for minimizing far-end noise coupling between interconnects in high-speed ceramic modules

In this paper, we present a methodology for minimizing far-end (FE) noise coupling between interconnects in high-speed ceramic modules. The high FE noise coupling between signal interconnects in ceramic modules has been a serious bottleneck for high-performance systems. A methodology employing power/ground mesh planes with minimized orthogonal lines and a via-connected coplanar-type shield (VCS) structure has been developed to minimize FE noise coupling between signal lines in ceramic modules. Optimized interconnect structure based on this methodology has demonstrated that the saturated FE crosstalk of a typical interconnect structure in ceramic modules could be reduced significantly by 88.7 %.

Crosstalk Analysis between Interconnects in High-Speed Server Packages

This paper discusses crosstalk analysis between interconnects in high-speed server packages. Over the last decade, the scaling of the CMOS transistors has enabled the design of microprocessors operating at multi-gigahertz frequencies. For meeting the high bandwidth demands and low-power requirements, digital technologies are quickly moving to gigabit data rate and sub-voltage range signaling levels. However, this higher speed performance comes at a price, which means that signal integrity becomes a significant portion of the design effort. Especially, crosstalk analysis between interconnects in high-speed packages has become critical for design optimization of signal interconnects in system. This paper investigates importance of crosstalk analysis for IBMs high-speed server packages. For an efficient crosstalk analysis between interconnects in highspeed digital systems, an IBMs internal tool called PATS (package analysis tool suite) was used to investigate crosstalk over 1000 signal nets. The ISNRR (integral of squared noise ramp response) method has been developed to quantify crosstalk accurately and used to analyze IBMs organic modules for high-speed applications.

Characterization of current signatures for microprocessors

This work presents current signatures for a set of test cases running on a general purpose server IBM POWER5/spl trade/ processor under the control of IBMs AIX/spl trade/ operating system. This is part of activities focused on understanding how to optimize the power delivery infrastructure with respect to total system cost. Specifically a better understanding of the current signatures of processors coupled with better understanding of how to design the decoupling infrastructure and in what ways the processor circuits are susceptible to power domain voltage noise is expected to help us accomplish this.

Channel Optimization for the Design of High Speed I/O links

The continuous increase in microprocessor performance demands an equal order of increase in the bandwidth requirements on the memory and I/O interfaces. Providing the required bandwidth at an acceptable cost is a challenge to the system packaging engineer. This paper discusseshow a passive channel can be optimized in a cost effective way to provide the maximum bandwidth. The paper focuses on the design methodology including modeling the channel, identifying the channel bottle-necks, optimizing around the bottle-necks and verifying the conclusions through simulation. Finally the simulation results are verified through hardware measurements.

Green initiative-power management and its effects on electronics packaging

The influence of Green initiatives and resulting reduction in power consumption have an impact on module reliability. In this paper we will discuss an approach that IBM is using to acquire and save cyclic field data from processors as well as the testing methodology used to quantify the reliability impacts of variable cyclic loads on FCPLGA packages. Important questions to be answered are: (1) what types of cyclic loads will IBM modules see in the field as a result of power management and applications run by our diverse customer set, and (2) what unique testing must be conducted to assure that there is no reliability exposure associated with said cyclic loads. This paper discusses new failure mechanisms found through minicycle stressing in a lab environment, meant to simulate cyclic loads that a processor would see in the field, where power was being throttled to control overall consumption. We will also discuss the methodology and implementation of a Figure of Merit algorithm which allows us to pull cyclic load histories on individual processors while in the field or from processors that have been returned to IBM.