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Dive into the research topics where Daniel Douriet is active.

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Featured researches published by Daniel Douriet.


electronic components and technology conference | 2007

Crosstalk Analysis between Interconnects in High-Speed Server Packages

Jinwoo Choi; Byron Krauter; Anand Haridass; Roger D. Weekly; Daniel Douriet; Sungjun Chun

This paper discusses crosstalk analysis between interconnects in high-speed server packages. Over the last decade, the scaling of the CMOS transistors has enabled the design of microprocessors operating at multi-gigahertz frequencies. For meeting the high bandwidth demands and low-power requirements, digital technologies are quickly moving to gigabit data rate and sub-voltage range signaling levels. However, this higher speed performance comes at a price, which means that signal integrity becomes a significant portion of the design effort. Especially, crosstalk analysis between interconnects in high-speed packages has become critical for design optimization of signal interconnects in system. This paper investigates importance of crosstalk analysis for IBMs high-speed server packages. For an efficient crosstalk analysis between interconnects in highspeed digital systems, an IBMs internal tool called PATS (package analysis tool suite) was used to investigate crosstalk over 1000 signal nets. The ISNRR (integral of squared noise ramp response) method has been developed to quantify crosstalk accurately and used to analyze IBMs organic modules for high-speed applications.


electronic components and technology conference | 2017

Package and Printed Circuit Board Design of a 19.2 Gb/s Data Link for High-Performance Computing

Sungjun Chun; Jose A. Hejase; Junyan Tang; Jean Audet; Dale Becker; Daniel M. Dreps; Glen A. Wiedemeier; Megan Nguyen; Lloyd A. Walls; Francesco Preda; Daniel Douriet

A 19.2 Gb/s per lane link with IBMs latest POWER8 processor module has been analyzed. This paper presents the overview of the high-speed link design from the signal integrity point of view. Design approaches in package and printed circuit board (PCB) to support the target data-rate have been discussed. The end-to-end communication bus is modeled from extracted post-route design with a 3-D full-wave extractor and has been simulated with IO properties at system level. Bath-tub curves are generated from data gathered in functioning systems running this 19.2 Gb/s link to confirm the operation of the link meets the required bit-error-rate criteria as the modeling and simulation predicted.


Archive | 2008

Method for detecting noise events in systems with time variable operating points

Daniel Douriet; Anand Haridass; Andreas Huber; Colm B. O'Reilly; Bao G. Truong; Roger D. Weekly


Archive | 2003

Method, apparatus and computer program product for implementing enhanced high frequency return current paths utilizing decoupling capacitors in a package design

Darryl John Becker; Daniel Douriet; Matthew S. Doyle; Andrew Benson Maki; Joel D. Ziegelbein


Archive | 2003

Method, structure, and computer program product for implementing high frequency return current paths within electronic packages

Darryl John Becker; Daniel Douriet; Matthew S. Doyle; Andrew Benson Maki; Joel D. Ziegelbein


Archive | 2006

Mitigate Power Supply Noise Response by Throttling Execution Units Based Upon Voltage Sensing

Daniel Douriet; Anand Haridass; Andreas Huber; Colm B. O'Reilly; Bao G. Truong; Roger D. Weekly


Archive | 2007

Method, apparatus, and computer program product for enhancing a power distribution system in a ceramic integrated circuit package

Daniel Douriet


Archive | 2008

Circuit substrate having post-fed die side power supply connections

Daniel Douriet; Francesco Preda; Brian L. Singletary; Lloyd A. Walls


Archive | 2007

Design Method and System for Minimizing Blind Via Current Loops

Daniel Douriet; Anand Haridass; Andreas Huber; Roger D. Weekly


Archive | 2008

Analyzing Impedance Discontinuities In A Printed Circuit Board

Daniel Douriet

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