Barend van Liempd

A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration

A software-defined radio receiver is presented, operating from 400 MHz to 6 GHz. The split front-end architecture has a low-band RF path (0.4-3 GHz) using 8-phase passive mixers and a high-band RF path (3-6 GHz) using 4-phase passive mixers. DC-offset, IIP 2, and harmonic recombination for harmonic rejection may be calibrated to achieve true wideband specifications. A 0.5-50 MHz tunable baseband bandwidth implies compliance with LTE and future standards. Despite having a 0.9 V supply, the receiver architecture ensures high out-of-band linearity. The 0.6 mm2, 28 nm CMOS receiver achieves down to 1.8 dB NF, >+3 dBm out-of-band IIP3, >70 dB calibrated HR3/5 and >+80 dBm calibrated IIP2. It tolerates 0 dBm blockers at 80 MHz offset with a blocker NF of 10 dB for a power consumption of 20-40 mW.

2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS

The electrical-balance (EB) duplexer concept explored in [1-4] suggests a possible integrated multiband alternative to conventional fixed-frequency surface-acoustic-wave (SAW) duplexers. The basic principle of the EB duplexer is to balance the impedances seen at the ports of a hybrid transformer to suppress signal transfer from the TX to the RX through signal cancellation (Fig. 2.2.1). While the potential payoff is tantalizing, several challenges must still be solved before EB duplexers can become commercially viable. Specifically, the duplexer must provide high isolation and linearity in both the TX and RX bands across wide bandwidth (BW), with low insertion loss (IL), all in the presence of a real antenna whose impedance is constantly varying due to real-world user interaction. In this paper, we present a duplexer that significantly advances the state-of-the-art for two of these critical challenges: linearity and insertion loss.

A +70-dBm IIP3 Electrical-Balance Duplexer for Highly Integrated Tunable Front-Ends

An electrical-balance duplexer achieving the state-of-the-art linearity and insertion loss (IL) performance is presented, enabled by a partially depleted RF silicon-on-insulator CMOS technology. A single-ended configuration avoids the common-mode isolation problem suffered by topologies with a differential low-noise amplifier. Highly linear switched capacitors allow for impedance balancing to antennas with <;1.5:1 voltage standing wave ratio from 1.9 to 2.2 GHz. +70-dBm input-referred third-order intercept point is achieved under high transmitter (TX) power (+30.5 dBm max.). TX IL is <;3.7 dB, and receiver IL is <;3.9 dB.

IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm

Fully integrated CMOS receivers achieve high linearity and low noise due to harmonic recombination but suffer from limited IIP2 and harmonic rejection due to mismatch and inaccuracies. This paper presents an 8-phase harmonic recombination receiver with independent IIP2 HR3 and HR5 calibration techniques. Calibrated >80dBm IIP2 >70dB HR3 and >75dB HR5 are measured.

Real-time RF self-interference cancellation for in-band full duplex

We demonstrate a real-time RF self-interference cancellation scheme for in-band full duplex using an electrical balance duplexer. The balance network in the duplexer has four 8-bit tunable capacitor banks, creating a four dimensional optimization space with over 4 billion settings. We present a particle swarm optimizer that is able to find a close to optimal solution within 1 ms. The goal of this demo is to show a self-interference cancellation scheme for very dynamic environments. More specifically our demo is able to mitigate instantaneous changes in the antenna impedance in order to keep the self-interference below the threshold.

An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power

When using electrical-balance duplexers (EBDs) to provide RF self-interference cancellation for in-band full-duplex, in-band distortion produced by nonlinear CMOS switches in the duplexer cause distortion that limits the headroom for additional self-interference cancellation in subsequent cancellation schemes in the transceiver. A prototype EBD is fabricated in 0.18μm SOI CMOS to investigate the dynamic range limitations of a transceiver architecture for next-generation wireless systems that supports in-band full-duplex and legacy FDD. Measurements show -85dBm in-band distortion at +10dBm TX input power, enough for short-range links at 10MHz BW.

A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection.

IM3-cancellation is a popular technique in LNAs to achieve very high linearity, but is also very sensitive to the exact device (bias) operating point. A 0.7-1.15GHz complementary common-gate LNA in 0.18μm silicon-on-insulator CMOS is presented that achieves good out-of-band (OOB) linearity without IM3-cancellation. Measurements of the 0.9mm2 prototype show a gain of >7dB, an NF of <;2.3dB, more than +15dBm OOB-IIP3 and over 0dBm B1dB. Compared to other work, this LNA has a similar or better linearity at only 10mW. The LNA uses a nominal supply of 2.5V, but was tested up to 3.7V and showed no significant degradation of its linearity for ±400mV supply variations. A power clamp, designed to enable testing at higher core supply voltage, withstands a >2.6kV HBM discharge, while the overall circuit is protected for >1kV HBM discharges.

A 0.7 to 1 GHz switched-LC N-Path LNA resilient to FDD-LTE self-interference at ≥40 MHz offset

This paper proposes a self-interference-resilient LNA for the FDD-LTE covering 0.7 to 1GHz. It incorporates a switched-LC N-path network with gain-boosting and optimum-biasing techniques to enhance the out-of-band (OOB) linearity at ≥40MHz offset. Implemented in 0.18µm SOI CMOS, the LNA achieves >31.2dB output rejection, +26.2dBm (+8dBm) OOB-IIP3 (iB1dB) at ≥40MHz offset and 6.8dB blocker NF at +4dBm blocker power for the default mode, while consuming a reasonable power of 48.4 to 62.5mW. When reconfigured to high-rejection mode, the LNA offers a tunable cancellation notch improving the output rejection to >50dBc.

A 0.7–1GHz tunable RF front-end module for FDD and in-band full-Duplex using SOI CMOS and SAW resonators

A 0.7–1GHz tunable front-end module (FEM) is presented for frequency-division duplexing and in-band full-duplex. It combines an electrical-balance duplexer (EBD) and tunable surface-acoustic wave resonators, demonstrating for the first time that these techniques are compatible and can be tuned independently. The EBD is integrated with a low-noise amplifier (LNA) in 0.18μm SOI CMOS and can operate with any antenna with a VSWR less than 2.3:1. The tunable FEM achieves more than 50dB dual-frequency isolation prior to the LNA, 2.6–3.4dB TX insertion loss and +58/+42dBm TX/RX-path out-of-band-IIP3, respectively. It has <8.8dB gain, with an input-referred, inband gain compression point up to +27.5dBm/+11dBm caused by TX leakage or blockers, respectively.

Nearly instantaneous collision and interference detection using in-band full duplex

In wireless communication it is assumed that transmitting nodes are unable to detect collisions. However, using recent advances in in-band full duplex, a system can be developed where the self-transmitted signal is sufficiently canceled in order to detect ongoing collisions. Enabling concurrent transmission and collision detection can greatly improve wireless communication by enhancing throughput and decreasing delay and energy consumption. For this demo, we implemented a real-time collision and interference detection algorithm on the FPGA of a USRP. Inband full duplex is enabled using an electrical balance duplexer. A second USRP is used to generate interfering signals on demand.