Bart Keppens

Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides

A novel diode-triggered SCR (DTSCR) ESD protection element is introduced for low-voltage application (signal, supply voltage /spl les/1.8 V) and extremely narrow ESD design margins. Trigger voltage engineering in conjunction with fast and efficient SCR voltage clamping is applied for the protection of ultra-sensitive circuit nodes, such as SiGe HBT bases (e.g. f/sub Tmax/=45 GHz in BiCMOS-0.35 /spl mu/m LNA input) and thin gate-oxides (e.g. tox=1.7 nm in CMOS-0.09 /spl mu/m input). SCR integration is possible based on CMOS devices or can alternatively be formed by high-speed SiGe HBTs.

ESD protection solutions for high voltage technologies

There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation issues and the creation of unexpectedly weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices.

SCR based ESD protection in nanometer SOI technologies

This paper introduces an SCR based ESD protection design for SOI technologies. It is explained how efficient SCR devices can be constructed in SOI. These devices outperform MOS devices by about 4 times. Experimental data from 65 nm and 130 nm SOI is presented to support this.

Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90nm technologies

This paper presents a novel active-source-pump (ASP) circuit technique to significantly lower the ESD sensitivity of ultrathin gate inputs in advanced sub-90nm CMOS technologies. As demonstrated by detailed experimental analysis, an ESD design window expansion of more than 100% can be achieved. This revives conventional ESD solutions for ultrasensitive input protection also enabling low-capacitance RF protection schemes with a high ESD design flexibility at IC-level. ASP IC application examples, and the impact of ASP on normal RF operation performance, are discussed.

ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies

This paper presents a protection strategy for ultra-sensitive I/O containing thin gate oxides, while combining two complementary ESD design approaches: (1) low-voltage diode-chain triggered SCR clamps that allow for efficient voltage clamping; (2) active-source-pump circuits applied for effective expansion of narrow ESD design windows for ultra-thin GOX protection. The focus of the paper is on the ASP schemes while some RF aspects are covered as well.

Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width scaling

A silicon-proven multi-finger turn-on (MFT) design technique that enables ESD width scaling combined with very low dynamic on-resistance is presented in various implementations. It can be applied to (self-protecting) drivers and/or ESD protection design. Using a novel merged ballast circuit design, very compact ESD protection configurations with an ESD area performance up to 5VHBM/um2 can be realized both in fully silicided and silicide blocked NMOS designs.

Low capacitive dual bipolar ESD protection

This paper presents a novel approach to reduce the parasitic capacitive loading of RF and high speed digital interfaces by up to 35%. Unlike in the classic dual diode protection, both junctions connected to the pad are used in every stress combination.