Markus Paul Josef Mergens

ESD protection solutions for high voltage technologies

There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation issues and the creation of unexpectedly weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices.

Advanced SCR ESD protection circuits for CMOS/SOI nanotechnologies

This paper reviews the application of SCR-based ESD protection circuits in advanced CMOS/SOI technologies. The devices are integrated in a flexible modular circuit design technique allowing for independent optimization of key characteristics. The IC application focus is on sensitive IOs, i.e. (ultra-)thin GOX input protection and robust output driver design using SCRs. Moreover, SCR transfer and integration into advanced SOI technologies is discussed. RF ESD principles are considered as well

Characterization and optimization of a bipolar ESD-device by measurements and simulations

Using an example of a bipolar transistor for ESD protection, we present new ways to incorporate a simulation tool chain into the design process. After calibration of the simulators, the best layout dimensions and well doping profiles could be evaluated. Differences in the devices switching behaviour under CDM and HBM stress conditions are demonstrated by transient device simulations. Finally, we outline a method to extract a set of parameters for a compact circuit model.

Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90nm technologies

This paper presents a novel active-source-pump (ASP) circuit technique to significantly lower the ESD sensitivity of ultrathin gate inputs in advanced sub-90nm CMOS technologies. As demonstrated by detailed experimental analysis, an ESD design window expansion of more than 100% can be achieved. This revives conventional ESD solutions for ultrasensitive input protection also enabling low-capacitance RF protection schemes with a high ESD design flexibility at IC-level. ASP IC application examples, and the impact of ASP on normal RF operation performance, are discussed.

ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies

This paper presents a protection strategy for ultra-sensitive I/O containing thin gate oxides, while combining two complementary ESD design approaches: (1) low-voltage diode-chain triggered SCR clamps that allow for efficient voltage clamping; (2) active-source-pump circuits applied for effective expansion of narrow ESD design windows for ultra-thin GOX protection. The focus of the paper is on the ASP schemes while some RF aspects are covered as well.

ESD-level circuit simulation-impact of gate RC-delay on HBM and CDM behavior

An extraction method for the effective gate RC-delay of MOS single- and multi-finger structures is introduced by deducing a rule of thumb for the effective poly resistance. In addition to the wiring and parasitic capacitance connected to a gate, this distributed poly resistance in conjunction with the nonlinear gate capacitance can cause an appreciable gate delay (RC/spl sim/1 ns). It is demonstrated for a CMOS output driver circuit that this effect is HBM relevant. Here, circuit simulations are compared to the corresponding TLP measurements. Furthermore, a general CDM-level circuit simulation methodology is presented. To our knowledge for the first time, a CDM current source model accounts for the single pin event character of CDM. Under such stress, the simulation reveals an unexpected large impact of the gate PC-delay formed by the metal interconnects in a CMOS double input inverter. Voltage overshoots occur at internal gates and lead to oxide breakdown, which was validated by CDM stress tests and physical failure analysis.

ESD-level circuit simulation impact of interconnect RC-delay on HBM and CDM behavior☆

Abstract An extraction method for the distributed, parasitic RC-elements of MOS single- and multi-fingers is introduced by deducing a rule of thumb for an effective poly resistance Reff. The lumped RC element described by the effective gate resistance in conjunction with the non-linear gate capacitance of the MOS model Cgate approximates sufficiently accurate the distributed RC elements of the gate in the ESD relevant time domain. In addition to the wiring and parasitic capacitance connected to a gate, this RC can cause a significant gate delay (RC∼1xa0ns) during ESD events. It is demonstrated for a CMOS output driver circuit that this effect is relevant for ESD switching behavior under human body model (HBM) stress. Here, circuit simulations are compared to the corresponding transmission line pulse (TLP) measurements. Furthermore, a general charge device model (CDM)-level circuit simulation methodology is presented. To our knowledge for the first time, a single-pin CDM event was simulated in a complex I/O circuit applying appropriate ESD models suitable for CDM simulation. Under such stress, the simulation reveals an unexpected large impact of the ‘gate’ RC-delay formed by metal interconnects in a CMOS double input inverter. Voltage overshoots occur at internal gates and lead to oxide breakdown. The failure signature was validated by CDM stress tests and physical failure analysis.

Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width scaling

A silicon-proven multi-finger turn-on (MFT) design technique that enables ESD width scaling combined with very low dynamic on-resistance is presented in various implementations. It can be applied to (self-protecting) drivers and/or ESD protection design. Using a novel merged ballast circuit design, very compact ESD protection configurations with an ESD area performance up to 5VHBM/um2 can be realized both in fully silicided and silicide blocked NMOS designs.

Novel design of driver and ESD transistors with significantly reduced silicon area

Abstract This paper presents three novel design techniques, which combined fulfill all major requirements posed on large driver and electrostatic discharge (ESD) protection transistors: minimum area consumption, good ESD robustness and optimized normal operation. Transistors protecting 5 V/μm 2 human body model were demonstrated. Significant silicon area reduction was demonstrated in deep-sub-micron CMOS, ranging from 0.35 μm down to 0.13 μm CMOS. This novel design solution follows standard design flows and does not require any process modifications.