Christian C. Russ

ESD protection solutions for high voltage technologies

There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation issues and the creation of unexpectedly weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices.

High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation ☆

This paper presents a novel SCR for power line and local I/O ESD protection. The HHI-SCR exhibits a dual ESD clamp characteristic: low-current high-voltage clamping and high-current low-voltage clamping. These operation modes enable latch-up immune normal operation as well as superior full chip ESD protection. The minimum latch current is controlled by device design. The HHI-SCR is demonstrated in 0.10um-CMOS and in a 0.4um-BiCMOS technology. The design is highly area efficient.

ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies

This paper presents a protection strategy for ultra-sensitive I/O containing thin gate oxides, while combining two complementary ESD design approaches: (1) low-voltage diode-chain triggered SCR clamps that allow for efficient voltage clamping; (2) active-source-pump circuits applied for effective expansion of narrow ESD design windows for ultra-thin GOX protection. The focus of the paper is on the ASP schemes while some RF aspects are covered as well.

Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width scaling

A silicon-proven multi-finger turn-on (MFT) design technique that enables ESD width scaling combined with very low dynamic on-resistance is presented in various implementations. It can be applied to (self-protecting) drivers and/or ESD protection design. Using a novel merged ballast circuit design, very compact ESD protection configurations with an ESD area performance up to 5VHBM/um2 can be realized both in fully silicided and silicide blocked NMOS designs.

Novel design of driver and ESD transistors with significantly reduced silicon area

Abstract This paper presents three novel design techniques, which combined fulfill all major requirements posed on large driver and electrostatic discharge (ESD) protection transistors: minimum area consumption, good ESD robustness and optimized normal operation. Transistors protecting 5 V/μm 2 human body model were demonstrated. Significant silicon area reduction was demonstrated in deep-sub-micron CMOS, ranging from 0.35 μm down to 0.13 μm CMOS. This novel design solution follows standard design flows and does not require any process modifications.

Novel fully silicided ballasting and MFT design techniques for ESD protection in advanced deep sub-micron CMOS technologies

Abstract A universal technique to design cost effective, fully silicided, high performance ESD devices is introduced [All rights reserved – Patents Pending]. This novel design solution can be implemented straightforwardly without process modifications. ESD performance levels obtained in different 0.25 and 0.18 μm CMOS technologies demonstrate that this technique can successfully replace silicide-blocked devices to achieve good ESD performance levels with economic silicon real estate consumption. In addition, a novel multi-finger turn-on design technique, which can be applied to both fully silicided and silicide-blocked designs (Patents Pending) is presented.