Koen Gerard Maria Verhaege

ESD protection solutions for high voltage technologies

There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation issues and the creation of unexpectedly weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices.

Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90nm technologies

This paper presents a novel active-source-pump (ASP) circuit technique to significantly lower the ESD sensitivity of ultrathin gate inputs in advanced sub-90nm CMOS technologies. As demonstrated by detailed experimental analysis, an ESD design window expansion of more than 100% can be achieved. This revives conventional ESD solutions for ultrasensitive input protection also enabling low-capacitance RF protection schemes with a high ESD design flexibility at IC-level. ASP IC application examples, and the impact of ASP on normal RF operation performance, are discussed.

ESD protection circuit design for ultra-sensitive IO applications in advanced sub-90nm CMOS technologies

This paper presents a protection strategy for ultra-sensitive I/O containing thin gate oxides, while combining two complementary ESD design approaches: (1) low-voltage diode-chain triggered SCR clamps that allow for efficient voltage clamping; (2) active-source-pump circuits applied for effective expansion of narrow ESD design windows for ultra-thin GOX protection. The focus of the paper is on the ASP schemes while some RF aspects are covered as well.

A compact model for the grounded-gate nMOS transistor behaviour under CDM ESD stress

Abstract The parasitic bipolar transistor inherent to grounded gate nMOS transistors is modelled, accounting for the specific conditions applied by CDM ESD stress. The avalanching of both, drain and source, the triggering of snapback and the CDM-specific bipolar saturation mode are addressed. Furthermore, a fast analytical method to determine CDM ESD lumped tester parasitics from measured pulse characteristics is presented. The triggering of the grounded gate nMOS transistor under CDM is studied in detail for different gate lengths. The optimal gate length for CDM protection in advanced submicron technologies is discussed.

Simulation study for the CDM ESD behaviour of the grounded-gate NMOS

The parasitic bipolar transistor inherent to grounded gate nMOSts is modelled accounting for the specific conditions applied by CDM ESD stress. The impact of the gate length on the CDM-specific bipolar saturation mode is addressed. The different operation modes occurring during CDM ESD stress translate to self-heating which explains the observed test results.

Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width scaling

A silicon-proven multi-finger turn-on (MFT) design technique that enables ESD width scaling combined with very low dynamic on-resistance is presented in various implementations. It can be applied to (self-protecting) drivers and/or ESD protection design. Using a novel merged ballast circuit design, very compact ESD protection configurations with an ESD area performance up to 5VHBM/um2 can be realized both in fully silicided and silicide blocked NMOS designs.

Novel design of driver and ESD transistors with significantly reduced silicon area

Abstract This paper presents three novel design techniques, which combined fulfill all major requirements posed on large driver and electrostatic discharge (ESD) protection transistors: minimum area consumption, good ESD robustness and optimized normal operation. Transistors protecting 5 V/μm 2 human body model were demonstrated. Significant silicon area reduction was demonstrated in deep-sub-micron CMOS, ranging from 0.35 μm down to 0.13 μm CMOS. This novel design solution follows standard design flows and does not require any process modifications.

Investigation into socketed CDM (SDM) tester parasitics

Abstract The ESD Association standards working group 5.3.2 is analyzing the procedure and stress that is applied to a device under test (DUT) using a socketed discharge model (SDM) test system, formerly referred to as socketed CDM. Our final goal is to define an SDM tester specification that will guarantee test result reproducibility across different test equipment. This paper investigates the effect of tester background parasitics on the discharge current waveforms of an SDM tester. Characteristic waveforms were studied and SDM testing was performed on actual devices. It is shown that SDM tester parasitics determine the stress applied to the DUT. This directly impacts the SDM failure threshold voltage levels and may lead to miscorrelation and non-reproducibility of test results across different SDM test systems. This paper empirically determines the relative contributions of the various tester parasitics to the total stress applied to the DUT. Our investigations indicate that the tester provides a 10–20 pF parasitic capacitance discharge into each pin of the device. Tester background parasitic elements play such an important role in the SDM discharge event that correlation between test systems built by different manufacturers is unlikely without completely duplicating a particular tester.

Component level ESD testing

This paper reviews different aspects of ESD component level testing. Traditional and alternate test methods are addressed. Focus topics are the device-under-test to tester interaction, the tester specifications and parasitics, the test procedures and test result reproduction and correlation. The purpose of the paper is to serve as a tutorial on the subject of Component Level ESD Testing.

Novel fully silicided ballasting and MFT design techniques for ESD protection in advanced deep sub-micron CMOS technologies

Abstract A universal technique to design cost effective, fully silicided, high performance ESD devices is introduced [All rights reserved – Patents Pending]. This novel design solution can be implemented straightforwardly without process modifications. ESD performance levels obtained in different 0.25 and 0.18 μm CMOS technologies demonstrate that this technique can successfully replace silicide-blocked devices to achieve good ESD performance levels with economic silicon real estate consumption. In addition, a novel multi-finger turn-on design technique, which can be applied to both fully silicided and silicide-blocked designs (Patents Pending) is presented.