Bart van Schravendijk

Integrated approach to improving local CD uniformity in EUV patterning

Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

METHODS OF ENCAPSULATION

Methods of encapsulation are provided. Methods and apparatuses suitable for depositing low hydrogen content, hermetic, thin encapsulation layers at temperatures less than about 300 DEG C are provided herein. The methods involve pulsing plasma while exposing a substrate to deposition reactants, and post-treating deposited encapsulation films to densify and reduce hydrogen content. Post-treatment methods include periodic exposure to inert plasma without reactants and exposure to ultraviolet radiation at a substrate temperature less than about 300 DEG C.

Cu electromigration improvement by adhesion promotion treatment (APT)

A new process to promote adhesion between the SiC diffusion barrier and Cu was developed to achieve significant improvement in electromigration of the Cu interconnect without sacrificing RC delay, line-to-line leakage, breakdown voltage and time-dependent-dielectric-breakdown. An in-situ treatment of the wafer surface inserted between the sequential processes of Cu pretreatment and SiC deposition increased the Cu/SiC interfacial adhesion by more than 30%. Electrical and physical characterization data is presented that demonstrates the improvement in reliability metrics of the interconnect using the newly developed process, while limiting the RC change to < 1%.

PDL oxide enabled pitch doubling

A double patterning (DP) process is introduced with application for advanced technology nodes. This DP technique is enabled by a novel low-temperature pulsed deposition layer (PDLTM) oxide film which is deposited directly on patterned photoresist. In this article, we will report the results of fabrication of sub-50nm features on a 100nm pitch by the PDL-spacer DP process using 0.85 NA dry ArF lithography. This result represents the potential of the PDL-based DP to significantly enhance the resolution of the patterning process beyond the limits of optical lithography. Components of CD variance for this spacer DP scheme will be discussed.