Tom Mountsier

Ti-based Barrier for Cu Interconnect Applications

After being forgotten for a number of years, Ti has recently re-gained attention for use in Cu barrier applications. For advanced logic products utilizing porous ultra low-k (ULK) dielectric, the main motivation of using a Ti-based barrier is that compared with a Ta-based barrier, the Ti-based barrier is more compatible with porous ULK due to its better resistance to the moisture associated with porous ULK films [1]. For memory products, the main driving force for switching from Ta to Ti is lower cost. Ti offers significantly lower cost of consumables (COC) than Ta. Regardless of product types, there is also a general interest in Ti due to its potential for reliability improvement. In this paper we present an approach of Ti-based barrier that not only addresses the known integration issues associated with Ti, but also demonstrates significant reliability improvement over a Ta-based barrier.

In-situ Formation of a Copper Silicide Cap For TDDB and Electromigration Improvement

Self-aligned barrier processes are being investigated as an alternative to standard dielectric barrier processes for the 65 nm technology nodes and beyond. Variations in the dielectric barrier process can modulate the copper-dielectric interface and the SiC/low k interface to improve dielectric and electromigration reliability. For the first time, in this paper, we will show that optimization of both the self aligned barrier and the SiC film can improve the adhesion between both the Cu and the dielectric layer on top, resulting in a 10-1000times increase in time-dependent dielectric breakdown lifetime

Work function tuning of plasma-enhanced atomic layer deposited WCxNy electrodes for metal/oxide/semiconductor devices

One of the main challenges facing the integration of metals as gate electrodes in advanced MOS devices is control over the Fermi level position at the metal/dielectric interface. In this study, we demonstrate the ability to tune the effective work function (EWF) of W-based electrodes by process modifications of the atomic layer deposited (ALD) films. Tungsten carbo-nitrides (WCxNy) films were deposited via plasma-enhanced and/or thermal ALD processes using organometallic precursors. The process modifications enabled us to control the stoichiometry of the WCxNy films. Deposition in hydrogen plasma (without nitrogen based reactant) resulted in a stoichiometry of WC0.4 with primarily W-C chemical bonding, as determined by x-ray photoelectron spectroscopy. These films yielded a relatively low EWF of 4.2 ± 0.1 eV. The introduction of nitrogen based reactant to the plasma or the thermal ALD deposition resulted in a stoichiometry of WC0.1N0.6–0.8 with predominantly W-N chemical bonding. These films produced a hi...

Advanced integrated metallization enables 3D-IC TSV scaling

Innovative solutions have been developed to address the challenges of through-silicon via (TSV) metallization with small sizes and high aspect ratios. We demonstrate an advanced metallization scheme including conformal film depositions of metal barrier and seed with excellent sidewall coverage to achieve void-free Cu fill in small-size (10 to 1 μm) TSV with high aspect ratio (10:1 to 20:1). In addition, it reduces the field metal thickness to significantly lower the costs of metallization and subsequent CMP. TSVs fabricated using this new process integration scheme exhibited higher breakdown voltage and lower leakage current than those made with the conventional PVD barrier seed. No degradation in performance was observed after 400°C annealing and thermal cycling. The improved performance is attributed to the formation of pinhole-free metal barrier layer with excellent sidewall coverage.

A comprehensive look at PVD scaling to meet the reliability requirements of advanced technology

The reliability of interconnects continues to be a formidable challenge as dimensions shrink from generation to generation. In this paper we demonstrate barrier/seed scaling, enabled by HCM® IONX PVD technology. We report high electromigration activation energy of ∼ 1 eV, and Jmax ≫ 6 MA/cm2, exceeding the ITRS 2007 requirements for the next several generations by a wide margin. Thinner barrier/seed with increased barrier etchback is shown to increase electromigration lifetime. Via stress migration results indicate that high barrier etchback is beneficial to reliability. TDDB results show a strong positive effect of barrier etchback on lifetime. We find that breakdown voltage for thinner barrier/seed is higher than that of the control. Breakdown voltage further increases with increased barrier etchback. For TDDB, the field acceleration coefficient, γ, improves with increased etch back from 4.3 (MV/cm)P−1 to 10 (MV/cm)−1 and the expected lifetime at operation conditions is improved by several orders of magnitude, exceeding requirements by a wide margin. This comprehensive study of PVD scalability proves a process space that provides the reliability margin necessary for continuing technology scaling for future generations.

Development of electroless Co via-prefill to enable advanced BEOL metallization and via resistance reduction

A novel metallization scheme was developed to enable advanced BEOL interconnect scaling. The proposed approach adopts electroless Co to selectively grow Co in vias, followed by conventional Cu metallization for the trench. We have demonstrated the feasibility of this approach through the process integration of electroless Co via pre-fill on a two metal layer interconnect test structure. A detailed discussion on the yield improvement, parametric data, and reliability will be presented in this paper.

An alternative approach to backside via reveal (BVR) for a via-middle through-Silicon via (TSV) flow

An alternative scheme has been developed to combine three major backside via reveal (BVR) processes, including (a) wafer polishing, (b) Si recess etching, and (c) wet clean, into an integrated wet etch process to replace the high cost chemical-mechanical planarization (CMP) and dry etching steps. The process combines two steps on a single-wafer platform: (1) bulk Si etching chemistry with high etch rate (>10 μm/min.) to replace the CMP or polishing and (2) selective Si etching chemistry (Si: SiO2 ~ 1800:1) to replace the Si recess dry etching step. Using this process, Si thickness uniformity can be significantly improved (for 20 μm Si removal), resulting in a lower variation in step height of through-Si via (TSV) protrusion across a 300 mm wafer. The overall cost is significantly lower than CMP plus dry etching. After the integrated wet etching process, passivation layers of low-temperature silicon nitride and oxide were deposited on the backside, followed by CMP to planarize the wafer and expose the Cu nails. The film adhesion is very good without showing any film delamination or peeling. This new integration scheme is robust with a wide process margin and provides cost savings over the conventional BVR flow.

Layout optimization and trade-off between 193i and EUV-based patterning for SRAM cells to improve performance and process variability at 7nm technology node

The Fin-FET Technology scaling to sub 7nm node, using 193 immersion scanner is restricted due to reduced margins for process. The cost of the process and complexity of designs is increasing due to multi-patterning to achieve area scaling using 193i scanner. In this paper, we propose a two Fin-cut mask design for Fin-pattering of 112 SRAM (two Fins for pull-down and one Fin for pull-up and pass-gate device) cell using 193i lithography and its comparison with EUVL single print. We also propose two keep masks for middle of line patterning ,with increased height of the SRAM cell using 193i, that results in area of a uniform-Fin SRAM cell area at 7nm technology; whereas EUVL can enable non-uniform SRAM cell at reduced area. Due to unidirectional patterning, margins for VIA0 landing over MOL are drastically reduced at 42nm gate pitch and hence to improve margins, the orientation for 1st metal is proposed to be orthogonal to the gate. This results in improved performance for SRAM and reliability of the technology.

Patterning with Amorphous Carbon Thin Films

Amorphous carbon hard mask films grown with plasma enhanced chemical vapor deposition are an enabling technology for advanced front-end-of-line patterning technologies. These films must have a low etch rate and be weakly roughened in dielectric etch chemistries, high transparency at lithography alignment wavelengths, and the mechanical properties to mitigate elastic instabilities such as line bending. The deposition process affects all of these parameters through the resulting structure and composition. Highly graphitic films deposited at 550°C are common; however, other process spaces relying on ion bombardment rather than temperature can create less graphitic films with improved film properties like transparency, hardness, and etch selectivity.

Process integration of iALD TaN for advanced Cu interconnects

A high density/low resistivity TaN film grown using ion-induced atomic layer deposition (iALD) has been developed as the metal barrier for nano-scale Cu interconnects. Excellent conformalilty and Cu barrier performance enable the use of thin iALD TaN as the metal barrier. Integration of this film has demonstrated improvement in line and via resistance while maintaining robust electromigration (EM), via stress migration (VSM), and dielectric reliability performance.