Bartomeu Alorda

Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination

Memory design in the nanometer regime imposes specific restrictions to the cell layout structure requiring regular disposition of transistors to minimize the impact of process parameter variations. These layout restrictions invalidate many of the traditional design techniques oriented to improve cell immunity to radiation-induced events that, in turn, get worsened with technology scaling. We analyze two design alternatives to improve cell hardening compatible with regular cell layouts providing an extensive analysis to illustrate the benefits of each technique. One of the proposed solutions is based on transistor width modulation that provides an immunity enhancement at the cost of a moderate cell-size increase. The other solution is based on multithreshold voltage selection showing a moderate immunity improvement at the cost of no impact on the cell area. The combination of both techniques is shown to be optimum when considering other design metrics like static noise margin, read/write stability, access time, and leakage. Results are demonstrated on 90- and 65-nm commercial technologies.

Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs

The main contribution of this work is providing a static and dynamic enhancement of bit-cell stability for low-power SRAM in nanometer technologies. We consider a wide layout topology without bends in diffusion layers for the nanometer SRAM cell design to minimize the impact of process variations. The design restrictions imposed by such a nanometer SRAM cell design prevents from applying traditional read SNM improvement techniques. We use the SNM as a measure of the cell stability during read operations, and Qcrit to quantify the robustness against SEE during hold mode. The techniques proposed have a low impact on read time and leakage current while improving significantly the SNM. Moreover, the Word-line modulation technique has no impact on strategic cell parameters like area and leakage when in hold mode. Results obtained from both a commercial 65nm CMOS technology and a 45nm BPTM technology are provided.

Critical charge characterization in 6-T SRAMs during read mode

In this work we analyze the effects of radiation-induced transient pulses on 6T SRAM cells operating in read mode. The critical charge of a memory cell during read mode is lower than in hold mode. For 1 to 0 upsets, this reduction reaches a factor x1.5 for events produced by alpha particles; this factor is even higher for longer induced current pulses. The impact of events propagated through the bit-lines is also analyzed. Results show that it is possible the occurrence of an upset in the Sense Amplifier producing a wrong output in the readout process without changing the memory cell stored value.

Defect oriented fault diagnosis for semiconductor memories using charge analysis: theory and experiments

We evaluated a diagnostic technique based on the charge delivered to the IC during a transition. Charge computed from the transient supply current is related to the circuit internal activity. A specific activity can be forced into the circuit using appropriate test vectors to highlight possible defect locations. Experimental results from a small test circuit and a 256 K SRAM demonstrate the experimental viability of the technique. The theoretical foundation is also discussed.

Charge based transient current testing (CBT) for submicron CMOS SRAMs

We analyze a transient current testing technique that measures and computes the charge delivered to the circuit during the transient operation. The method was applied to 0.5 /spl mu/m CMOS SRAMs that passed various logic tests. Results indicate that charge based testing (CBT) can successfully test submicron ICs since it tolerates large and variable background currents, can be applied to non-fully static circuits, and clearly shows outlier parts. CBT is a sensitive physical test correlating transient charge injected to the properties of particular transistors that switch during selected patterns. This gives CBT an efficient diagnostic capability. A compact hardware module to compute CBT was demonstrated previously.

An Experimental Approach to Accurate Alpha-SER Modeling and Optimization Through Design Parameters in 6T SRAM Cells for Deep-Nanometer CMOS

We report a detailed analysis about the memory soft error rate (SER) dependence with transistor design parameters for six-transistor (6T) SRAM cells fabricated on a 65-nm CMOS commercial technology. SER data are obtained from accelerated test with an Am-241 alpha source. Five 6T cells with different nMOS and pMOS transistors size combinations were fabricated and characterized. After verifying that transistor width increase always provides higher critical charge values, SER data show that this value is improved only when increasing the pMOS transistors width. Memory cells containing non-minimum-width nMOS transistors always exhibit worse SER values than cells with minimum-size ones. In addition, one cell with a higher Qcrit than another can show a worse SER depending on the transistor type whose size is being enlarged. Accordingly to this, we have found that SER may be increased by 76% without modifying cell structure nor impacting cell area. This behavior is qualitatively and quantitatively explained through an analytical model that relates SER to Qcrit and the transistor design parameters.

Word-line power supply selector for stability improvement of embedded SRAMs in high reliability applications

Embedded SRAM yield dominates the overall ASIC yield, therefore the methodologies centered on improving SRAM cell stability will be introduced in the design as a mandatory. Word-line voltage modulation has showed that it is possible to improve cell stability during access operations. The high variability of physical and performance parameters introduce the need to adopt adaptable solutions to adequately improve SRAM cell stability. In this work, we present a wordline voltage selector circuit designed to modulate power-supply word-line voltage at each individual embedded SRAM block. The final area overhead is minimal and several strategies can be implemented with the embedded SRAM allowing adjust wordline voltage value during the life of ASIC, taking into account different operation, aging and degradations effects.

Analysis of radiation-hardening techniques for 6T SRAMs with structured layouts

We analyze two complementary radiation-hardening techniques for 6T SRAM memories compatible with structured layouts. One approach relies on the individual selection of the threshold voltage of each of the four transistors forming the cross-coupled inverters of the SRAM cell. The other one is based on the modification of the widths of all pmos or all nmos transistors of the cell. The first technique does not affect the cell layout. The second one increases the minimum width of all pmos by a factor cp and the minimum width of all nmos by a factor cn. This prevents the formation of diffusion bends, allowing structured layouts. Both techniques provide an improvement in SEU robustness.

A Two-Level Power-Grid Model for Transient Current Testing Evaluation

We evaluate the possibilities of transient current testing practical implementation by comparing the transient supply current signature at the IC supply pins to its internal behavior. This analysis is key to correlate the internal circuit block transient current shape to the waveform measured outside the IC. These waveforms may differ significantly due to the power supply grid, whose capacitive and inductive components can modify both the frequency and magnitude components of the transient current. Given the complexity of today ICs, an accurate description of the circuit power grid is required to investigate the merits of transient current testing (idd(t)) approaches. In this work we develop and analyze a hierarchical power-grid equivalent circuit to evaluate the supply current frequency components and their distribution over the power/ground grid hierarchy. This is a key step to determine the feasibility of on-chip vs. off-chip idd(t) strategies and their posterior application to on-line testing.

An off-chip sensor circuit for on-line transient current testing

We propose and evaluate an architecture of an integrated transient current off-chip monitor to facilitate implementation of transient current based testing of CMOS VLSI circuits. The monitor measures the transient current idd(t) by sensing the voltage drop at a resistor and provides the charge delivered to the circuit (i.e. the area under the waveform) as the test observable. Designed in 0.18 /spl mu/m CMOS technology, the sensor measures the transient supply current and provides the waveform area (i.e. the charge delivered to the circuit). The transient current is measured at the circuit supply rail, by sensing the voltage drop at a resistor connected between the IC supply PIN and the voltage source as shown in Figure 1.