Bencherki Mebarki

Self-Aligned Double Patterning Process for 32/32nm Contact/Space and beyond using 193 Immersion Lithography

State of the art production single print lithography for contact is limited to ~43-44nm half-pitch given the parameters in the classic photolithography resolution formula for contacts in 193 immersion tool (k1 ≥ 0.3, NA = 1.35, and λ = 193nm). Single print lithography limitations can be overcome by (1) Process / Integration based techniques such as double-printing (DP), and spacer based self-aligned double patterning (SADP), (2) Non-standard printing techniques such as electron-beam (eBeam), extreme ultraviolet lithography (EUVL), nano-imprint Lithography (NIL). EUV tools are under development, while nanoimprint is a developmental tool only. Spacer based SADP for equal line/space is well documented as successful patterning technique for 3xnm and beyond. In this paper, we present an adaptation of selfaligned double patterning process to 2-D regular 32/32nm contact/space array. Using SADP process, we successfully achieved an equal contact/space of 32/32nm using 193 immersion lithography that is only capable of 43-44nm resolvable half-pitch contact printing. The key and unique innovation of this work is the use of a 2-D (x and y axis) pillar structure to achieve equal contact/space. Final result is a dense contact array of 32nm half-pitch in 2-D structure (x and y axis). This is achieved on simplified stack of Substrate / APF / Nitride. Further transfer of this new contact pattern from nitride to the substrate (e.g., Oxide, APF, Poly, Si...) is possible. The technique is potentially extendible to 22/22nm contact/space and beyond.

Barrier Integrity Effect on Leakage Mechanism and Dielectric Reliability of Copper/OSG Interconnects

In this paper, we investigate the effect of copper diffusion barrier integrity on the leakage behavior and dielectric reliability of copper/micro porous organo-silica-glass (OSG) interconnects. Significant differences in the field dependence of TDDB median-time-to-failure are observed when comparing sub-critical and sealing barriers. Also for the temperature acceleration of TDDB, a significant difference is found which is reflected in the thermal activation energies. With fast voltage ramp measurements, I-V curves of samples with subcritical and sealing barriers are compared before and after constant current stresses. Above 1.4 MV/cm, the dominant leakage mechanism is found to be Frenkel-Poole emission regardless of barrier treatments and stress times. Below 1.4 MV/cm, however, the I-V characteristic is modulated by the barrier integrity, which can be attributed to copper diffusion into the intermetal dielectric.

Impact of process decisions and alignment strategy on overlay for the 14nm node

For the 14nm node and beyond there are many integration strategy decisions that need to be made. All of these can have a significant impact on both alignment and overlay capability and need to be carefully considered from this perspective. One example of this is whether a Litho Etch Litho Etch (LELE) or a Self Aligned Double Patterning (SADP) process is chosen. The latter significantly impacting alignment and overlay mark design. In this work we look at overlay performance for a Back End of Line (BEOL) SADP Dual Damascene (DD) process for the 14nm node. We discuss alignment mark design, particularly focusing on the added complexity and issues involved in using such a process, for example design of the marks in the Metal Core and Keep layers and recommend an alignment scheme for such an integration strategy.