Christopher S. Ngai

Novel and cost-effective multiple patterning technology by means of invisible SiOxNy hardmask

The Cost of Ownership (CoO) for semiconductor processing has been primarily dominated by lithography. In multiple patterning processes, additional materials and the impact to throughput of multiple patterning passes appear to become additional major contributors to manufacturing cost as well. We introduce SiOxNy hardmask as a new memorization layer for multiple patterning that addresses the non-lithographic cost contributor to manufacturing. The optical constants of the SiOxNy hardmask are matched to those of the photoresist at the imaging wavelength, and that makes it invisible at the exposure wavelength, enabling lithography directly over the hardmask topography, while at the same time it will be visible to those wavelengths that are used for alignment and overlay. The SiOxNy hardmask is inserted below the photoresist which will make the rework and integration schemes much simpler and result in cost savings by replacing only photoresist layers during multiple patterning processes. Additionally, by eliminating the need for traditional spincast planarization and the associated tri-layer etch we can improve the critical dimension uniformity (CDU) and reduce proximity contributions from etch, and their respective etch proximity corrections. In this work, we engineered the lithographic stack to be compatible with the invisible SiOxNy hardmask. Lithographic process windows, CDU, and LER/LWR are compared with conventional tri-layer stack and we demonstrate triple patterning memorized into the SiOxNy hardmask after which patterns are then transferred, at once, into the bottom integrated stack. Finally, major benefits of using the invisible hardmask on device scaling and patterning challenges are discussed, such as for LE2, LE3, and trench and cut patterning.

Self-Aligned Double Patterning Process for 32/32nm Contact/Space and beyond using 193 Immersion Lithography

State of the art production single print lithography for contact is limited to ~43-44nm half-pitch given the parameters in the classic photolithography resolution formula for contacts in 193 immersion tool (k1 ≥ 0.3, NA = 1.35, and λ = 193nm). Single print lithography limitations can be overcome by (1) Process / Integration based techniques such as double-printing (DP), and spacer based self-aligned double patterning (SADP), (2) Non-standard printing techniques such as electron-beam (eBeam), extreme ultraviolet lithography (EUVL), nano-imprint Lithography (NIL). EUV tools are under development, while nanoimprint is a developmental tool only. Spacer based SADP for equal line/space is well documented as successful patterning technique for 3xnm and beyond. In this paper, we present an adaptation of selfaligned double patterning process to 2-D regular 32/32nm contact/space array. Using SADP process, we successfully achieved an equal contact/space of 32/32nm using 193 immersion lithography that is only capable of 43-44nm resolvable half-pitch contact printing. The key and unique innovation of this work is the use of a 2-D (x and y axis) pillar structure to achieve equal contact/space. Final result is a dense contact array of 32nm half-pitch in 2-D structure (x and y axis). This is achieved on simplified stack of Substrate / APF / Nitride. Further transfer of this new contact pattern from nitride to the substrate (e.g., Oxide, APF, Poly, Si...) is possible. The technique is potentially extendible to 22/22nm contact/space and beyond.

Development of amorphous silicon based EUV hardmasks through physical vapor deposition

Extending extreme ultraviolet (EUV) single exposure patterning to its limits requires more than photoresist development. The hardmask film is a key contributor in the patterning stack that offers opportunities to enhance lithographic process window, increase pattern transfer efficiency, and decrease defectivity when utilizing very thin film stacks. This paper introduces the development of amorphous silicon (a-Si) deposited through physical vapor deposited (PVD) as an alternative to a silicon ARC (SiARC) or silicon-oxide-type EUV hardmasks in a typical trilayer patterning scheme. PVD offers benefits such as lower deposition temperature, and higher purity, compared to conventional chemical vapor deposition (CVD) techniques. In this work, sub-36nm pitch line-space features were resolved with a positive-tone organic chemically-amplified resist directly patterned on PVD a-Si, without an adhesion promotion layer and without pattern collapse. Pattern transfer into the underlying hardmask stack was demonstrated, allowing an evaluation of patterning metrics related to resolution, pattern transfer fidelity, and film defectivity for PVD a-Si compared to a conventional tri-layer patterning scheme. Etch selectivity and the scalability of PVD a-Si to reduce the aspect ratio of the patterning stack will also be discussed.