Benjamin R. Buhrow

Low-power W-band CPWG InAs/AlSb HEMT low-noise amplifier

We present the development of a low-power W-band low-noise amplifier (LNA) designed in a 200-nm InAs/AlSb high electron mobility transistor (HEMT) technology fabricated on a 50-mum GaAs substrate. A single-stage coplanar waveguide with ground (CPWG) LNA is described. The LNA exhibits a noise figure of 2.5 dB and an associated gain of 5.6 dB at 90 GHz while consuming 2.0 mW of total dc power. This is, to the best of our knowledge, the lowest reported noise figure for an InAs/AlSb HEMT LNA at 90 GHz. Biased for maximum gain, the single-stage amplifier presents 6.7-dB gain and an output 1-dB gain compression point (P1dB) of -6.7dBm at 90 GHz. The amplifier provides broad-band gain, greater than 5dB over the entire W-band

Block Cipher Speed and Energy Efficiency Records on the MSP430: System Design Trade-Offs for 16-Bit Embedded Applications

Embedded microcontroller applications often experience multiple limiting constraints: memory, speed, and for a wide range of portable devices, power. Applications requiring encrypted data must simultaneously optimize the block cipher algorithm and implementation choice against these limitations. To this end we investigate block cipher implementations that are optimized for speed and energy efficiency, the primary metrics of devices such as the MSP430 where constrained memory resources nevertheless allow a range of implementation choices. The results set speed and energy efficiency records for the MSP430 device at 132 cycles/byte and 2.18 \(\upmu \mathrm {J/block}\) for AES-128 and 103 \(\mathrm {cycles/byte}\) and 1.44 \(\upmu \mathrm {J/block}\) for equivalent block and key sizes using the lightweight block cipher SPECK. We provide a comprehensive analysis of size, speed, and energy consumption for 24 different variations of AES and 20 different variations of SPECK, to aid system designers of microcontroller platforms optimize the memory and energy usage of secure applications.

System level approach for assessing and mitigating differential skew for 10+ Gbps SerDes applications

Weave-induced skew on printed wiring boards (PWB) for 10+ Gbps SerDes data rates can be very significant. In this paper, we not only investigate weave-induced skew but also look at other sources of skew. We show the weave skew results taken from measurements of three different test boards. Results from a fourth board are presented to examine PWB differential via skew. Measurements from a fifth board are analyzed to determine total channel skew. We propose a budget such that a certain amount of skew can be tolerated with a small increase in channel insertion loss. We then present a case study to project overall performance on PWB yield. We observe a number of anomalies with our test results and suggest additional studies to guard against unpredicted high skew.

Ka-band (35 GHz) 3-stage SiGe HBT low noise amplifier

We present design, simulation, and measurement of a Ka-band (35 GHz) low noise amplifier (LNA) fabricated in a 120 GHz f t /f m a x SiGe BiCMOS technology (IBM 7HP). To our knowledge, this is the first demonstration of a Ka-band LNA in a SiGe technology, representing the first of a set of desired building blocks for integrating a Ka-band transmit and receive (T/R) module in a single chip environment. At 35 GHz, the 3-stage LNA exhibited 15.1 dB gain, -5.9 dBm output compression (P1dB), 9 dBm third order intercept (IP3), and 5.6 dB noise figure at 25.6 mW DC power. Peak gain and bandwidth of the LNA were found to be 19.0 dB and 10.7 GHz respectively at a center frequency of 31.3 GHz.

An X-band hybrid MIC feedforward amplifier for low residual noise operation

A 10 GHz, 15 dB gain feedforward amplifier (FFA) is described whose design is primarily aimed at reducing residual phase noise. The two-module hybrid MIC construction incorporates GaAs MMICs and microstrip thin-film interconnects on alumina. For loop balance electronic gain control is achieved using dual gate distributed amplifiers, while phase control is accomplished with mechanical phase shifters and delay lines. Measurements of near carrier noise are made from 1 Hz to 6.4 MHz. In the flicker region the 1 Hz intercept is -110 dBc/Hz, with an approximate corner frequency around 30 KHz at -160 dBc/Hz.

A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols

The Advanced Encryption Standard (AES) together with the Galois Counter Mode (GCM) of operation has been approved for use in several high throughput network protocols to provide authenticated encryption. However, the demand for continued increase in network bandwidth has not abated and we anticipate the need for continual performance improvement of AES-GCM in hardware. Additionally, as data interfaces become wider and segmented, existing methods of GCM parallelization become inefficient. This paper presents a novel scalable architecture for highly parallel implementations of AES-GCM that can process multiple separately-keyed packets simultaneously every clock cycle. We demonstrate throughputs of 482 Gb/s in a single Xilinx Virtex Ultrascale FPGA and describe how the architecture can be used to achieve over 800 Gb/s in a system comprising multiple FPGAs.

1 Tb/s anti-replay protection with 20-port on-chip RAM memory in FPGAs

As network data rates advance toward 1 Tb/s, hardware-based implementations of anti-replay offer desirable tradeoffs over software. However, internal logic busses in FPGAs are becoming wider (512+ bits) and segmented (more than one packet per clock cycle) to accommodate increased network data rates. Such busses are challenging for applications such as anti-replay that require read-modify-write operations to a coherent database on each packet arrival. In this paper we present an FPGA-targeted pipelined anti-replay design capable of accommodating 1024 IPsec tunnels at 1 Tb/s data rate. The novel design is enabled by fast on-chip block RAMs in a xcvu190 Virtex Ultrascale FPGA that are used to construct a 20-port RAM memory operating at 400 MHz with over 5 Tb/s of peak bandwidth. Custom single-clock write-combining techniques are described that accommodate multiple concurrent updates to the same database address. We also investigate the limits of capacity and concurrency for the anti-replay application.

Simulated imaging of atherosclerotic & radiofrequency ablation lesions using phase subtraction

Cardiovascular diseases are the main cause of death worldwide. Atherosclerosis and atrial fibrillation are structural and electrical pathophysiology, respectively, that can lead to acute events such as stroke or myocardial infarction. We used particle-based Monte Carlo methods to simulate X-ray phase imaging of atherosclerotic plaque types IV-VIII in the aorta, iliac, and coronary arteries. We also assessed scar lesion development in radiofrequency catheter ablation treatment of atrial fibrillation by simulating lesions 2, 5, 10, 30, and 60 days post-procedure. For both applications, we found high signal-to-noise and contrast-to-noise ratios in all lesions. These results suggest that X-ray phase imaging is a viable technique for non-invasive quantitative cardiovascular lesion characterization.