Barry K. Gilbert

High-frequency characterization of power/ground-plane structures

In this paper, we describe a strategy to characterize power and ground-plane structures using a full cavity-mode frequency-domain resonator model. We develop insights into modal analysis and introduce a novel technique to suppress modal impedances, minimizing both transfer and input impedances. The influence of port locations on the Z matrix is evaluated.

Single event effects in circuit-hardened SiGe HBT logic at gigabit per second data rates

This attempt at circuit level single event effects (SEE) hardening of SiGe HBT logic provides the first reported indication of the level of sensitivity in this important technology, Characterization over data rate up to 3 Gbps and over a broad range of heavy ion LETs provides important clues to upset mechanisms and implications for upset rate predictions. We augment ion test data with pulsed laser SEE testing to indicate the sensitive targets within the circuit and to provide insights into the upset mechanism(s),.

12 GHz clocked operation of ultralow power interband resonant tunneling diode pipelined logic gates

We report on the successful demonstration of a functionally complete set of logic gates based on resonant interband tunneling diodes (RITDs) with a maximum operating frequency in excess of 12 GHz. At this high frequency of operation, the power dissipation is remarkably low-on the order of 0.5 mW per gate. The circuits for all gates, AND, OR, XOR, and INV, shared the same layout geometry, consisting of two Schottky diodes and three RITDs. Logical functionality was determined solely by varying the relative areas of the devices.

Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self test (CREST)

SEE testing at multi-Gbit/s data rates has traditionally involved elaborate high speed test equipment setups for at-speed testing. We demonstrate a generally applicable self test circuit approach implemented in IBMs 5AM SiGe process, and describe its ability to capture complex error signatures during circuit operation at data rates exceeding 5 Gbit/s. Comparisons of data acquired with FPGA control of the CREST ASIC versus conventional bit error rate test equipment validate the approach. In addition, we describe SEE characteristics of the IBM 5AM process implemented in five variations of the D flip-flop based serial register. Heavy ion SEE data acquired at angles follow the traditional RPP-based analysis approach in one case, but deviate by orders on magnitude in others, even though all circuits are implemented in the same 5AM SiGe HBT process.

Self-aligned InP DHBT with f/sub /spl tau// and f/sub max/ over 300 GHz in a new manufacturable technology

We report self-aligned indium-phosphide double-heterojunction bipolar transistor devices in a new manufacturable technology with both cutoff frequency (f/sub /spl tau//) and maximum oscillation frequency (f/sub max/) over 300 GHz and open-base breakdown voltage (BV/sub ceo/) over 4 V. Logic circuits fabricated using these devices in a production integrated-circuit process achieved a current-mode logic ring-oscillator gate delay of 1.95 ps and an emitter-coupled logic static-divider frequency of 152 GHz, both of which closely matched model-based circuit simulations.

Description and evaluation of the FAST-Net smart pixel-based optical interconnection prototype

The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses a reflective optical system to globally interconnect a multichip array of smart pixel devices. The three-dimensional optical system links each chip directly to every other with a dedicated bidirectional parallel data path. in the experiments, several prototype smart-pixel devices were packaged on a common multichip module (MCM) with interchip registration accuracies of 5-10 /spl mu/m. The smart-pixel arrays (SPAs) consist of clusters of oxide-confined vertical-cavity surface-emitting lasers and photodetectors that are solder bump-bonded to Si integrated circuits. The optoelectronic elements are arranged within each cluster on a checkerboard pattern with 125-/spl mu/m pitch. The experimental global optical interconnection module consists of a mirror and lens array that are precisely aligned to achieve the required interchip parallel connections between up to 16 SPAs. Five prototype SPAs were placed on the MCM to allow the evaluation of a variety of interchip links. Measurements verified the global link pattern across several devices on the MCM with high optical resolution and registration. No crosstalk between adjacent channels was observed after alignment. The I/O density and efficiency results suggest that a multi-terabit switch module that incorporates global optical interconnection to overcome conventional interconnection bottlenecks is feasible.

Heavy-ion broad-beam and microprobe studies of single-event upsets in 0.20-/spl mu/m SiGe heterojunction bipolar transistors and circuits

Combining broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response of digital SiGe HBT technology. This new understanding of the SEU mechanisms shows that the right rectangular parallel-piped model for the sensitive volume is not applicable to this technology. A new first-order physical model is proposed and calibrated with moderate success.

The Dynamic Spatial Reconstructor A Computed Tomography System for High-Speed Simultaneous Scanning of Multiple Cross Sections of the Heart*

A new generation whole-body computed tomography system has been developed to provide accurate visualization and measurement of the vital functions of the heart, lungs, and circulation. This dynamic spatial reconstructor system (DSR) provides stop-action (01-sec), rapidly sequential (60-per-second), synchronous volume (240 simultaneous adjacent 1-mm-thick transaxial sections) reconstructions and display of the full anatomic extents of the internal and external surfaces of the heart throughout successive cardiac cycles, and will permit visualization of the three-dimensional vascular anatomy and circulatory functions in all regions of the body of patients with cardiovascular and other circulatory disabilities.

An SEU hardening approach for high-speed SiGe HBT digital logic

A new circuit-level single-event upset (SEU) hardening approach for high-speed SiGe HBT current-steering digital logic is introduced and analyzed using both device and circuit simulations. The workhorse D-type flip-flop circuit architecture is modified in order to significantly improve its SEU immunity. Partial elimination of the effect of cross-coupling at the transistor level in the storage cell of this new circuit decreases its vulnerability to SEU. The SEU response of this new circuit is quantitatively compared with three other D flip-flop architectures, including the unhardened circuit, a conventional NAND gate based circuit, and a current-sharing hardened (CSH) circuit, at both variable data rate and switching current. The new circuit shows substantial improvement in SEU response over the unhardened version, with little increase in layout complexity and power consumption. While the NAND gate based circuit still shows better SEU response than the other circuits, its high power consumption will preclude its use in space applications. Our results suggest that this new circuit architecture exhibits sufficient SEU tolerance, low layout complexity, and modest power consumption, and thus should prove suitable for many space applications requiring very high-speed digital logic.

InAs/AlSb/GaSb resonant interband tunneling diodes and Au-on-InAs/AlSb-superlattice Schottky diodes for logic circuits

Integrated resonant interband tunneling (RIT) and Schottky diode structures, based on the InAs/GaSb/AlSb heterostructure system, are demonstrated for the first time. The RIT diodes are advantageous for logic circuits due to the relatively low bias voltages (/spl sim/100 mV) required to attain peak current densities in the mid-10/sup 4/ A/cm/sup 2/ range. The use of n-type InAs/AlSb superlattices for the semiconducting side of Schottky barrier devices provides a means for tailoring the barrier height for a given circuit architecture. The monolithically integrated RIT/Schottky structure is suitable for fabrication of a complete diode logic family (AND, OR, XOR, INV).