Erik S. Daniel

Modeling, Design, Fabrication, and Performance of Rectangular μ-Coaxial Lines and Components

A miniature non-uniform copper-air rectangular coaxial line with the inner conductor supported by periodic dielectric straps is demonstrated. The overall height of the line is 310mum with the outer conductor cross-section being 250mumtimes250mum. The measured loss is 0.22dB/cm at 26GHz, while the isolation between two parallel lines with a center-to-center separation of 700mum is better than 60dB. Several quasi-planar components are designed and fabricated on the same wafer, and presented here are a branch-line hybrid and a transmission line resonator. The through and coupled port transmissions for the hybrid at 26GHz are -3.25dB and -3.35dB respectively, with phase misbalance below 0.2deg. The transmission line resonator has an unloaded Q-factor of 110 at 25GHz

Accurate resistance, inductance, capacitance, and conductance (RLCG) from uniform transmission line measurements

Existing time-based and frequency-based RLCG extraction methods from measurements on uniform transmission lines are discussed. Using a THRU bisect de-embedding technique proved useful in removing resonances, particularly with the distributed resistance.

A 20 GS/s 5-Bit SiGe BiCMOS Dual-Nyquist Flash ADC With Sampling Capability up to 35 GS/s Featuring Offset Corrected Exclusive-Or Comparators

The design and wafer probe test results of a 5-bit SiGe flash ADC are presented. The integrated circuit, fabricated in a 200/250 GHz fT/Fmax, SiGe BiCMOS technology, provides a 5-bit analog to digital conversion with dual Nyquist operation at sample frequencies up to 20 GHz. Sampling clock rates are demonstrated as high as 35 GS/s. The ADC makes use of a comparator with an integrated exclusive-or function to reduce power consumption. The device also generates two half-rate interleaved outputs to ease data capture with laboratory equipment. An effective number of bits (ENOB) of nearly 5.0 is achieved for low-frequency input tones, dropping to 4.0 at 10 GHz.

A 20Gb/s SerDes transmitter with adjustable source impedance and 4-tap feed-forward equalization in 65nm bulk CMOS

The design and wafer probe test results of a 20 Gb/s Source-Series Terminated SerDes transmitter are presented. The integrated circuit, fabricated in a 65 nm bulk CMOS technology, transmits pre-emphasized data through the use of a 4-tap feed-forward equalizer. Transmitter output impedance is adjustable from 45 to 55 ohms. A power consumption of 167 mW at 1.1 V was measured at a transmit rate of 20 Gb/s.

A 35 GS/s 5-Bit SiGe BiCMOS flash ADC with offset corrected exclusive-or comparator

The design and wafer probe test results of a 5-bit SiGe ADC are presented. The integrated circuit, fabricated in a 200/250 GHz fT/Fmax, SiGe BiCMOS technology, provides a 5-bit analog to digital conversion with input tone frequencies up to 20 GHz and sampling clock rates up to 35 GS/s. The ADC makes use of a comparator with an integrated exclusive-or function to reduce power consumption. The device also generates two half-rate interleaved outputs to ease in data capturing with laboratory equipment. An effective number of bits (ENOB) of nearly 5.0 is achieved for low frequency input tones, dropping to 4.0 at 10 GHz.

Design of a Compact System Using a MEMS Accelerometer to Measure Body Posture and Ambulation

Interest in studying human posture, movement, and physical activity is growing due in part to the increasing prevalence of obesity. Accelerometers are commonly used in motion analysis systems to enable researchers to conduct studies outside of the traditional laboratory environment; however the available systems tend to be bulky and unsuitable for long-term studies. Therefore, a need exists for a physically robust, yet compact motion analysis system that can be easily worn for an extended time period without disrupting the persons range of motion. Here we describe our on-going efforts to develop a robust, compact system that can measure body posture and movement using a tri-axial accelerometer, and then store this data on a secure digital memory card. This device can be easily configured to collect accelerometer data for specific applications in human motion analysis. In the future, this device will be used to study physical activity in free-living individuals

Block Cipher Speed and Energy Efficiency Records on the MSP430: System Design Trade-Offs for 16-Bit Embedded Applications

Embedded microcontroller applications often experience multiple limiting constraints: memory, speed, and for a wide range of portable devices, power. Applications requiring encrypted data must simultaneously optimize the block cipher algorithm and implementation choice against these limitations. To this end we investigate block cipher implementations that are optimized for speed and energy efficiency, the primary metrics of devices such as the MSP430 where constrained memory resources nevertheless allow a range of implementation choices. The results set speed and energy efficiency records for the MSP430 device at 132 cycles/byte and 2.18 (upmu mathrm {J/block}) for AES-128 and 103 (mathrm {cycles/byte}) and 1.44 (upmu mathrm {J/block}) for equivalent block and key sizes using the lightweight block cipher SPECK. We provide a comprehensive analysis of size, speed, and energy consumption for 24 different variations of AES and 20 different variations of SPECK, to aid system designers of microcontroller platforms optimize the memory and energy usage of secure applications.

Ka-Band SiGe HBT Power Amplifier for Single-Chip T/R Module Applications

We present the development of a Ka-band (28-33 GHz) power amplifier designed in a 200/250 GHz fT/fmax, SiGe BiCMOS technology (IBM 8HP). A 4-way microstrip-based power amplifier using on-chip Wilkinson power combiners is described. To our knowledge, this is the first demonstration of a Ka-band power amplifier in SiGe technology designed for integration into a single-chip transmit/receive (T/R) module. The power amplifier exhibits a -10 dB compression point (PlOdB) of 19.4 dBm and a -1 dB compression point (PldB) of 15.4 dBm. The maximum gain of the amplifier is 46.8 dB at 31.9 GHz with a -3 dB bandwidth of 4.7 GHz.

Coming Challenges with Terabit-per-Second Data Communication

The growth in network data-rates is outpacing several constituent technologies, which is creating new challenges that cannot be readily overcome through simple extensions of previous approaches. This paper contributes by identifying new challenges facing the emerging data-communication protocols in the 400 Gb/s to 1 Tb/s range. Three particular challenges are presented along with their respective design implications and options: off-chip data interfaces; on-chip data busses; and off-chip buffering.

Design of Posture and Activity Detector (PAD)

In recent years, there has been much research and development of wearable devices using accelerometers for studying physical activity. Previously, we have described the development of the Posture and Activity Detector (PAD). After demonstrating success with PAD, we were motivated to improve the design by taking the device one step further and implementing all of these components on a single printed circuit board, adding a few additional features to make the system more flexible, and custom-designing an outer case. We have continued our efforts in improving PAD with respect to software development as well as making PAD more physically robust and mass producible. In this paper, the specifications for PAD will be outlined including its hardware and software components, and clinical research applications.