Barbara A. Randall

Single event effects in circuit-hardened SiGe HBT logic at gigabit per second data rates

This attempt at circuit level single event effects (SEE) hardening of SiGe HBT logic provides the first reported indication of the level of sensitivity in this important technology, Characterization over data rate up to 3 Gbps and over a broad range of heavy ion LETs provides important clues to upset mechanisms and implications for upset rate predictions. We augment ion test data with pulsed laser SEE testing to indicate the sensitive targets within the circuit and to provide insights into the upset mechanism(s),.

Heavy-ion broad-beam and microprobe studies of single-event upsets in 0.20-/spl mu/m SiGe heterojunction bipolar transistors and circuits

Combining broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response of digital SiGe HBT technology. This new understanding of the SEU mechanisms shows that the right rectangular parallel-piped model for the sensitive volume is not applicable to this technology. A new first-order physical model is proposed and calibrated with moderate success.

An SEU hardening approach for high-speed SiGe HBT digital logic

A new circuit-level single-event upset (SEU) hardening approach for high-speed SiGe HBT current-steering digital logic is introduced and analyzed using both device and circuit simulations. The workhorse D-type flip-flop circuit architecture is modified in order to significantly improve its SEU immunity. Partial elimination of the effect of cross-coupling at the transistor level in the storage cell of this new circuit decreases its vulnerability to SEU. The SEU response of this new circuit is quantitatively compared with three other D flip-flop architectures, including the unhardened circuit, a conventional NAND gate based circuit, and a current-sharing hardened (CSH) circuit, at both variable data rate and switching current. The new circuit shows substantial improvement in SEU response over the unhardened version, with little increase in layout complexity and power consumption. While the NAND gate based circuit still shows better SEU response than the other circuits, its high power consumption will preclude its use in space applications. Our results suggest that this new circuit architecture exhibits sufficient SEU tolerance, low layout complexity, and modest power consumption, and thus should prove suitable for many space applications requiring very high-speed digital logic.

Application of RHBD Techniques to SEU Hardening of Third-Generation SiGe HBT Logic Circuits

Shift registers featuring radiation-hardening-by-design (RHBD) techniques are realized in IBM 8HP SiGe BiCMOS technology. Both circuit and device-level RHBD techniques are employed to improve the overall SEU immunity of the shift registers. Circuit-level RHBD techniques include dual-interleaving and gated-feedback that achieve SEU mitigation through local latch-level redundancy and correction. In addition, register-level RHBD based on triple-module redundancy (TMR) versions of dual-interleaved and gated-feedback cell shift registers is also realized to gauge the performance improvement offered by TMR. At the device-level, RHBD C-B-E SiGe HBTs with single collector and base contacts and significantly smaller deep trench-enclosed area than standard C-B-E-B-C devices with dual collector and base contacts are used to reduce the upset sensitive area. The SEU performance of these shift registers was then tested using heavy ions and standard bit-error testing methods. The results obtained are compared to the unhardened standard shift register designed with CBEBC SiGe HBTs. The RHBD-enhanced shift registers perform significantly better than the unhardened circuit, with the TMR technique proving very effective in achieving significant SEU immunity

A comparison of SEU tolerance in high-speed SiGe HBT digital logic designed with multiple circuit architectures

The single-event upset (SEU) responses of three D flip-flop circuits, including two unhardened, and one current-sharing hardened (CSH) circuit, are examined using device and circuit simulation. The circuit that implements the conventional D flip-flop logic using standard bipolar NAND gates shows much better SEU performance than the other two. Cross coupling at transistor level in the storage cell of the other two circuits increases their vulnerability to SEU. The observed differences are explained by analyzing the differential output of the emitter coupled pair being hit. These results suggest a potential path for achieving sufficient SEU tolerance in high-speed SiGe heterojunction bipolar transistor (HBT) digital logic for many space applications.

Emerging multigigahertz digital and mixed-signal integrated circuits targeted for military applications: dependence on advanced electronic packaging to achieve full performance

A revolution is occurring in several device and integrated circuit technologies (silicon CMOS and its extensions such as silicon germanium and silicon on insulator [SOI] and the so-called III-V compound semiconductors including indium phosphide and gallium arsenide), as well as in solid-state sensors such as infrared detectors enabled by the new materials and devices. These new components are being used to enhance the performance of many systems, and even to create systems never before available, of present interest to the U.S. Department of Defense and of likely near-term interest to parts of the commercial electronics industry such as the landline, wireless, and satellite telecommunications industry. These new components require advanced electronic packaging that does not restrict or degrade their performance. Unfortunately largely due to commercial cost pressures, research in and small-lot manufacture of high-performance packaging though still feasible and not lacking for good ideas for possible enhancement, are no longer being actively pursued either by the principal U.S. government agencies (e.g., DARPA, Air Force), by the commercial electronic packaging industry, or by commercial consortia such as the Microelectronics and Computer Technology Corporation (defunct as of June 2000), Semiconductor Research Corporation (SRC), or Sematech Inc. This paper discusses recent examples of high-performance components and integrated circuit technologies and describes how they are being exploited in new or upgraded systems. Advances in packaging technology that will be required to support the new integrated circuits are also described. In conclusion, several possible approaches are reviewed by which the United States can regain momentum in the development of performance-driven packaging technologies.

Ka-Band SiGe HBT Power Amplifier for Single-Chip T/R Module Applications

We present the development of a Ka-band (28-33 GHz) power amplifier designed in a 200/250 GHz fT/fmax, SiGe BiCMOS technology (IBM 8HP). A 4-way microstrip-based power amplifier using on-chip Wilkinson power combiners is described. To our knowledge, this is the first demonstration of a Ka-band power amplifier in SiGe technology designed for integration into a single-chip transmit/receive (T/R) module. The power amplifier exhibits a -10 dB compression point (PlOdB) of 19.4 dBm and a -1 dB compression point (PldB) of 15.4 dBm. The maximum gain of the amplifier is 46.8 dB at 31.9 GHz with a -3 dB bandwidth of 4.7 GHz.

Ka-band (35 GHz) 3-stage SiGe HBT low noise amplifier

We present design, simulation, and measurement of a Ka-band (35 GHz) low noise amplifier (LNA) fabricated in a 120 GHz f t /f m a x SiGe BiCMOS technology (IBM 7HP). To our knowledge, this is the first demonstration of a Ka-band LNA in a SiGe technology, representing the first of a set of desired building blocks for integrating a Ka-band transmit and receive (T/R) module in a single chip environment. At 35 GHz, the 3-stage LNA exhibited 15.1 dB gain, -5.9 dBm output compression (P1dB), 9 dBm third order intercept (IP3), and 5.6 dB noise figure at 25.6 mW DC power. Peak gain and bandwidth of the LNA were found to be 19.0 dB and 10.7 GHz respectively at a center frequency of 31.3 GHz.

High-speed, low-power digital and analog circuits implemented in IBM SiGe BiCMOS technology

Under the auspices of Defense Advanced Research Project Agency Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being explored by Mayo include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation by Mayo to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS technology are presented.

Implementation of a gallium arsenide multichip digital circuit operating at 500-1000 MHz clock rates using a Si/Cu/SiO/sub 2/ MCM-D technology

Two different deposited multichip modules (MCMs) were fabricated in nCHIPs nC3000 Si/Cu/SiO/sub 2/ process. The first of these MCMs was a passive test coupon containing a variety of microstrip and stripline transmission line structures, allowing the measurement of dc and ac signal amplitude losses in long conductors, as well as assessments of crosstalk and reflections as functions of line dimensions and spacings. The second MCM incorporated sixteen Gallium Arsenide (GaAs) integrated circuits, all designed to work together at clock rates in the hundreds of MHz; all components were attached, face up, with an aluminum wire bonding process. The design, fabrication, assembly and test processes for these modules will be described, as well as the lessons learned about this MCM process for the design of subsystems up to the high hundreds of MHz clock rates.