Bernhard Sell

Charge-based capacitance measurements (CBCM) on MOS devices

A new simple method of measuring capacitance-voltage characteristics of MOS devices is presented. Proceeding from the charge-based capacitance measurement technique suggested recently, a compact test structure with high resolution has been developed, which only requires measurement of do quantities. The method was tested on a 0.6-/spl mu/m CMOS process with small and large area capacitors and compared to well-known high-frequency capacitance-voltage results. Beside using a reference structure, a second means of extracting parasitic effects is demonstrated for small structures. The test structure allows measurements in a wide frequency range with high accuracy and low noise contribution at small capacitance levels.

Chemical vapor deposition of tungsten silicide (WSix) for high aspect ratio applications

Abstract Chemical vapor deposition of tungsten silicide into high aspect ratio trenches has been investigated using a commercial 8-inch Applied Materials Centura single wafer deposition tool. For an in-depth study of both step coverage and stoichiometry, a combined chemistry/topography simulator has been developed. Dichlorosilane reduction of tungsten hexafluoride (WF6) has been identified as a suitable chemistry to fill deep trenches with tungsten disilicide, while for WF6 reduction with silane (SiH4) or disilane (Si2H6) fundamental drawbacks have been identified for extreme aspect ratios. In the process range under study, good agreement is observed between the simulated step coverages and those obtained from scanning electron microscope images. The simulations predict a deposition regime in which both good step coverage and a suitable stoichiometry are achieved inside deep trenches.

Interfaces characteristics between tungsten silicide electrodes and thin dielectrics

Abstract In today’s ULSI technology there is an increasing demand in metal electrodes for storage capacitors and transistors. In this publication we present an investigation of MOS capacitor structures with CVD tungsten silicide (WSi x ) as metal electrode in conjunction with silicon dioxide (SiO 2 ) and oxidized nitride (NO). Bulk silicon and poly silicon were used as second electrode, respectively. Tungsten silicide has been used both as gate electrode and as bottom electrode. For both cases thermal stability up to 780°C with low leakage current has been shown. Band discontinuities between SiO 2 and WSi x were estimated from current–voltage measurements.

Experimental study and modeling of the temperature dependence of soft breakdown conduction in ultrathin gate oxides

In this work, we focus our interest on the temperature dependence of soft breakdown conduction (SBD), mainly in the range in which real devices are commonly operated (-20/spl deg/C<T<160/spl deg/C). A thorough experimental study involving samples with different oxide thicknesses and substrate types is presented, and the results are interpreted in terms of an extended version of the quantum point contact model (QPC) for the non-zero temperature case. Even though several approaches attempting to explain the SBD I-V characteristics have been proposed, analytical modeling of its temperature dependence has always been restricted to a single bias condition. In contrast, we provide a simple parameterization of the experimental data which accounts for both I-V and I-T characteristics within a consistent framework based on the physics of mesoscopic conductors. The magnitude of the current flowing through the SBD spot essentially depends on the barrier height encountered by incoming electrons, while the shape of the I-V characteristics is dictated by the particular features of the spot and the potential drop distribution.

Temperature Dependence of the Hard Breakdown Current of MOS Capacitors

I-V curves as a function of temperature of broken down n and p-type MOS capacitors with different oxide thicknesses are presented. In accumulation, a crossover of the temperature dependent curves is observed. At low voltages the hard breakdown current increases with temperature whereas it decreases with temperature for higher voltages. This behaviour can be straightforwardly linked to the available charge for conduction at the electrodes. MINIMOS simulations as well as theoretical considerations were performed that clearly support this idea.

Fast interface characterization of tunnel oxide MOS structures

As new gate materials become increasingly interesting in conjunction with tunnel oxides, a fast and reliable interface characterization technique becomes indispensable. Fast turnaround times require a method which can be applied to simple test structures like planar capacitors. For the first time, we demonstrate an automatic extraction of physical oxide thickness and flatband potential from capacitance-voltage measurements which includes quantum confinement effects and Fermi-Dirac statistics. Automatic extraction is necessary for uniformity analysis across a whole wafer. New gate materials are typically binary or ternary alloys where the interface to the gate dielectric is very sensitive to deposition parameters. Such systems are likely to show higher nonuniformities than polysilicon electrodes. An example is presented where polysilicon gates exhibit a uniformity in flatband potential within a wafer of less than /spl plusmn/15 mV while a thickness variation of 0.1 nm has been observed.

Interface analysis of atomic layer deposited-TiN gate electrodes on ultrathin SiO2 layers

As new gate materials become increasingly interesting in conjunction with tunnel oxides, new deposition techniques have to be developed that deposit thin metal layers without degrading the gate dielectric. Recently, atomic layer deposition has been identified as a suitable method to deposit refractory metal alloys with well-defined properties. For the first time, a recently developed automated characterization of capacitance–voltage (C–V) curves is employed to identify challenges during the initiation of a metal atomic layer deposition process. While some problems were eliminated by adapting the deposition process, others will require further process or tool modifications to reduce the nonuniformities observed within each wafer. The temperature dependence of the C–V curves indicates an unintended titanium-rich layer at the interface, which disappears after annealing above 800 °C. A further development of the surface pretreatment and subsequent deposition will be necessary to avoid this phenomenon. In this...