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Dive into the research topics where Matthias Goldbach is active.

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Featured researches published by Matthias Goldbach.


european solid state device research conference | 2010

Carbon junction implant: Effect on leakage currents and defect distribution

Guntrade Roll; Stefan Jakschik; Matthias Goldbach; Thomas Mikolajick; L. Frey

In this paper we present a detailed investigation on the influence of carbon co-implantation in the source/drain extension on leakage current and defect density in PFET transistors. Carbon is used to reduce the transient enhanced boron diffusion, to decrease short channel effects and to control the overlap length of the transistor. Leakage currents are measured and separated in order to analyze the influence of the carbon on the different MOSFET regions. An increase in carbon dose by a factor of 1.15 leads to an enhanced source/drain extension leakage which is caused by carbon induced defects. No effect of the carbon implantation on source/drain junction leakage was found as the co-implant is located above the source/drain depletion region. In addition an increase of gate induced drain leakage with carbon dose was observed. This increase is further analyzed by charge pumping technique.


Proceedings of SPIE | 2008

Gate edge roughness in electron beam direct write and its influence to device characteristics

Kang-Hoon Choi; Rok Dittrich; Matthias Goldbach; C. Hohle; Katja Keil; Thomas Marschner; Mark Tesauro; F. Thrum; Roy Zimmermann; Johannes Kretz

Line edge roughness (LER) and line width roughness (LWR) have raised questions and concerns as current lithography techniques reduce critical dimensions (CD) below 50 nm. There are few applications of controlled variation of LER and LWR, even among those which use electron beam direct writing (EBDW), although it is highly desirable to test the influence of systematical variation of LER and LWR on actual semiconductor devices. To get a clear understanding how and what the LERs and LWRs are influencing in EBDW, we have designed and fabricated transistor gates with programmed LER and LWR using EBDW and observed those based on CD-SEM metrology. The obtained results including calculated power spectrum density (PSD) shows the capability of EBDW to control the LER/LWR. Further, the influence of edge/width roughness in EBDW on device characteristics is reviewed and it gives how the effect of LWR/LER translates to device performance in DRAM process flow. It is found that the control of LWR is more important than that of LER for future lithography developments.


Archive | 2005

Process for vertically patterning substrates in semiconductor process technology by means of inconformal deposition

Thomas Hecht; Matthias Goldbach; Uwe Schröder


Archive | 2004

Method for fabricating a memory cell

Matthias Goldbach; Thomas Mikolajick; Albert Birner


Archive | 2004

Method of forming a silicon dioxide layer

Albert Birner; Matthias Goldbach; Irene Sperl


Archive | 2003

Method for fabricating trench capacitors for integrated semiconductor memories

Matthias Goldbach; Jörn Lützen; Andreas Orth


Archive | 2004

Transistor structure, memory cell, DRAM, and method for fabricating a transistor structure in a semiconductor substrate

Matthias Goldbach; Ulrich Frey; Björn Fischer


Archive | 2008

Method of manufacturing integrated circuits including a FET with a gate spacer and a fin

Matthias Goldbach; Jessica Hartwich; Lars Dreeskornfeld; Arnd Scholz; Tobias Mono


Archive | 2004

Method for forming a trench in a layer or a layer stack on a semiconductor wafer

Uwe Schroeder; Matthias Goldbach; Tobias Mono


Archive | 2002

Stress-reduced layer system

Matthias Goldbach; Bernhard Sell; Annette Sänger

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Thomas Mikolajick

Dresden University of Technology

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