Dirk Schumann

Fast interface characterization of tunnel oxide MOS structures

As new gate materials become increasingly interesting in conjunction with tunnel oxides, a fast and reliable interface characterization technique becomes indispensable. Fast turnaround times require a method which can be applied to simple test structures like planar capacitors. For the first time, we demonstrate an automatic extraction of physical oxide thickness and flatband potential from capacitance-voltage measurements which includes quantum confinement effects and Fermi-Dirac statistics. Automatic extraction is necessary for uniformity analysis across a whole wafer. New gate materials are typically binary or ternary alloys where the interface to the gate dielectric is very sensitive to deposition parameters. Such systems are likely to show higher nonuniformities than polysilicon electrodes. An example is presented where polysilicon gates exhibit a uniformity in flatband potential within a wafer of less than /spl plusmn/15 mV while a thickness variation of 0.1 nm has been observed.

Suppression of the Reverse Short Channel Effect in (Sub-)0.25um nMOSFETs using elevated S/D structures

nMOSFETs with elevated S/D structures were fabricated by selective epitaxial growth of in-situ doped S/D regions. Variation of the total thermal budget allowed the optimization of outdiffusion from the epi-Si with respect to the realization of shallow junctions. For all process conditions investigated the Reverse Short Channel Effect (RSCE) was completely suppressed indicating that the RSCE observed for conventional processed nMOSFETs has to be attributed to S/D implantation. The process presented allows a realization of typical advantages for elevated S/D structures with an optimized Vth roll-off.