H.-M. Rein

Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s

In this paper, design aspects of high-speed digital and analog ICs are discussed which allow the designer to exhaust the high-speed potential of advanced Si-bipolar technologies. Starting from the most promising circuit concepts and an adequate resistance level, the dimensions of the individual transistors in the ICs must be optimized very carefully using advanced transistor models. It is shown how the bond inductances can be favourably used to improve circuit performance and how the critical on-chip wiring must be taken into account. Moreover, special modeling aspects and ringing problems, caused by emitter followers, are discussed. An inexpensive mounting technique is presented which proved to be well suited up to 50 Gb/s, the highest data rate ever achieved in any IC technology. The suitability of the design aspects discussed is confirmed by measurements of digital circuits and broadband amplifiers developed for 10 and 40 Gb/s optical-fiber links.

Millimeter-wave VCOs with wide tuning range and low phase noise, fully integrated in a SiGe bipolar production technology

Millimeter-wave voltage-controlled oscillators (VCOs) are presented which are fully integrated in a SiGe bipolar production technology. The low-cost differential circuits have been designed and optimized for low phase noise and wide tuning range. As an example, by varying the bias voltage of the on-chip varactor, the oscillation frequency can be changed from 36 to 46.9 GHz (i.e., by 26%). In this wide frequency range, phase noise between -107 and -110dBc/Hz at 1-MHz offset frequency and single-ended voltage swing of about 0.95V/sub pp/ /spl plusmn/10% (differential: 1.9V/sub pp/) were measured. The circuit consumes 280mW at -5.5-V supply voltage. The high oscillation frequency and low phase noise at wide tuning range are record values for fully integrated oscillators in Si-based technologies. The basic oscillator was then extended by a cascode stage as an output buffer. Now the VCO performance is no longer degraded if nonperfectly terminated transmission lines are driven. Thus, the chip can be mounted in a low-cost socket; however, at the cost of increased phase noise and power consumption.

Influence of impact-ionization-induced instabilities on the maximum usable output voltage of Si-bipolar transistors

The onset of impact-ionization-induced instabilities limits the operating range of Si-bipolar transistors, especially in power stages. Therefore, analytical relations which characterize the onset of instabilities are derived for different driving conditions (mainly V/sub BE/=const. and I/sub E/=const.) and arbitrary transistor geometries. They allow the designer and technologist to calculate the maximum usable dc output voltage in dependence on transistor dimensions and technological parameters. As a consequence, the voltage range above BV/sub CE0/ can now be more intensively and reliably used and thus the performance potential of a given technology can be better exploited. However, the reduction of the maximum tolerable output voltage with increasing emitter (or collector) current must be carefully considered. The presented theory and analytical results are verified by three-dimensional (3-D) transistor simulations and by measurements.

Modeling substrate effects in the design of high-speed Si-bipolar ICs

In the design of high-speed ICs, the influence of the substrate on circuit performance must be considered carefully. Therefore, in this paper the contribution of the p/sup -/ substrate and channel stopper to the equivalent circuits of Si-bipolar transistors and bond pads are theoretically and experimentally investigated up to very high frequencies. Improved equivalent substrate circuits, well suited for standard circuit simulators (e,g., SPICE), are derived and checked by numerical simulation using a new simulator (called SUSI). The validity of both the numerical simulation results and the equivalent circuits are verified by on-wafer measurements up to 20 GHz. Finally, the simulator was successfully applied to investigate noise coupling via the substrate.

120-Gb/s VCSEL-based parallel-optical interconnect and custom 120-Gb/s testing station

A 120-Gb/s optical link (12 channels at 10 Gb/s/ch for both a transmitter and a receiver) has been demonstrated. The link operated at a bit-error rate of less than 10/sup -12/ with all channels operating and with a total fiber length of 316 m, which comprises 300 m of next-generation (OM-3) multimode fiber (MMF) plus 16 m of standard-grade MMF. This is the first time that a parallel link with this bandwidth at this per-channel rate has ever been demonstrated. For the transmitter, an SiGe laser driver was combined with a GaAs vertical-cavity surface-emitting laser (VCSEL) array. For the receiver, the signal from a GaAs photodiode array was amplified by a 12-channel SiGe receiver integrated circuit. Key to the demonstration were several custom testing tools, most notably a 12-channel pattern generator. The package is very similar to the commercial parallel modules that are available today, but the per-channel bit rate is three times higher than that for the commercial modules. The new modules demonstrate the possibility of extending the parallel-optical module technology that is available today into a distance-bandwidth product regime that is unattainable for copper cables.

Multi-gigabit-per-second silicon bipolar ICs for future optical-fiber transmission systems

Basic silicon bipolar ICs for use in systems operations at bit rates of about 2.5 Gb/s are described. Examples are multiplexers, demultiplexers, amplifiers, decision circuits, etc. It is shown that the speed requirements can be met (for nearly all circuits) by todays standard technologies, provided that appropriate circuit concepts are used and the circuits are designed carefully. Applying todays advanced bipolar technologies with self-aligning polysilicon processes, bit rates well above 10 Gb/s are achievable in several cases. >

Modeling and measurement of substrate coupling in Si-bipolar IC's up to 40 GHz

Parasitic substrate coupling can severely degrade the performance of high-speed ICs and must be considered carefully in circuit design. Therefore, this paper proposes several equivalent circuits that are well suited for modeling substrate coupling up to very high frequencies with standard circuit simulators such as SPICE. Their element values can be calculated for arbitrary layout configurations from numerical simulations (using our SUbstrate SImulator SUSI), which are based on experimentally determined, specific technological/electrical data. The validity of both the simulator and the equivalent circuits has been verified by on-wafer measurements up to 40 GHz, the highest frequency reported so far for modeling of substrate coupling. For this, special test structures were designed and fabricated in an advanced Si-bipolar technology. This work is focused on substrate modeling in very-high-speed rather than in complex ICs.

A versatile Si-bipolar driver circuit with high output voltage swing for external and direct laser modulation in 10 Gb/s optical-fiber links

A monolithic integrated driver circuit developed for laser modulation in a 10 Gb/s optical-fiber link is presented. The IC was fabricated in a self-aligned double-polysilicon Si-bipolar production technology with f/sub T//spl ap/25 GHz. The circuit can be operated up to 14 Gb/s with a maximum output voltage swing as high as 3.6 V at 50 /spl Omega/ load (corresponding to an internal current swing of 108 mA), which allows the circuit to drive external modulators. In addition, the circuit can be used for direct laser modulation at 10 Gb/s, since the output current swing can easily be controlled over a wide range (e.g., from 15 mA to 60 mA). Problems in the design of such driver circuits as well as their solutions are discussed in detail. >

SiGe Bipolar VCO With Ultra-Wide Tuning Range at 80 GHz Center Frequency

A SiGe millimeter-wave VCO with a center frequency around 80 GHz and an extremely wide (continuous) tuning range of 24.5 GHz ( ap 30%) is presented. The phase noise at 1 MHz offset is -97 dBc/Hz at the center frequency (and less than -94 dBc/Hz in a frequency range of 21 GHz). The maximum total output power is about 12 dBm. A cascode buffer improves decoupling from the output load at reasonable VCO power consumption (240 mW at 5 V supply voltage). A low-power frequency divider (operating up to 100 GHz) provides, in addition, a divided-by-four signal. As a further intention of this paper, the basic reasons for the limitation of the tuning range in millimeter-wave VCOs are shown and the improvement by using two (instead of one) varactor pairs is demonstrated.

A simple method for separation of the internal and external (peripheral) currents of bipolar transistors

Abstract A simple method is described which enables the direct base and collector current of a bipolar transistor each to be separated into an internal and external (peripheral) part. Such a separation is, e.g. a necessary precondition for evaluating the reduction of current gain with decreasing emitter size and, furthermore, for estimating the effective internal base resistance as well as the emitter-current crowding due to the voltage drop across this resistance. The method described is based on very careful measurements of test transistors with different emitter geometries. The approach was experimentally verified with double-implanted high-speed transistors (transit frequency f T ⋍ 7 GHz ). For example, an emitter stripe width of about 2 μm leads to the following results: About 32% of the base current but only 9% of the collector current flow outside the emitter area defined by the implantation mask, resulting in a reduction of the common-emitter current gain to about 75% of its internal value.