Bertrand Borot

Validated 90nm CMOS technology platform with low-k copper interconnects for advanced system-on-chip (SoC)

This paper presents a complete 90nm CMOS technology platform dedicated to advanced SoC manufacturing, featuring 16/spl Aring/ EOT-70nm transistors (standard process) or 21/spl Aring/-90nm transistors (Low Power process) as well as 2.5 or 3.3V I/O transistors, copper interconnects and SiOC low-k IMD (k=2.9). The main critical process steps are described and electrical results are discussed. Moreover, using advanced lithographic tools, fully functional 1 Mbit SRAM instances, based on a highly manufacturable 6T 1.36/spl mu/m/sup 2/ memory cell, have been processed. The cell is detailed and its features, both electrical and morphological, are discussed.

Predictive Delay Evaluation on Emerging CMOS Technologies: A Simulation Framework

The main goal of this paper is to study the delay evolution for future technology nodes (32 nm and beyond) using electrical circuit predictive simulations. With this aim, two SPICE predictive models, directly based on ITRS data, are developed for devices and for interconnect respectively. The predictive spice models generation is presented and validated versus 45 nm silicon data. The predictive delay evaluation is performed with buffered interconnect lines simulations. The simulation results show that the critical interconnect length should be in the order of 10 mum for the 2020 generation. Moreover, in forthcoming technologies, driver resizing and systematic buffer insertion will no longer be sufficient to systematically limit wire delay increase.

Test Structure for Process and Product Evaluation

The objective of this paper is to present a test structure introduced in the scribe lines designed to detect process drift and to characterize product performances, i.e. delay and VDDmin. A brief overview of the structure, designed in a ST-Microelectronics 130nm technology, is given. The main advantages of the structure are to be introduced in the scribe line and to have a complex architecture close to the product back-end configurations. A specific test flow is applied to the structure in order to extract relevant data (frequency, delay and bias). The monitoring efficiency of the structure is validated with measurement correlation performed on the structure data, parametric test data and full test chip data.

Using Model for Assessment of Complementary Metal Oxide Semiconductor Technology and Roadmaps as a Pre-Simulation Program with Integrated Circuit Emphasis Model Generator for Early Technology and Circuit Simulation

In this work, we show how to use the model for assessment of CMOS technology and roadmaps (MASTAR) in order to generate ready-to-use simple pre-simulation program with integrated circuit emphasis (pre-SPICE) data. Calibration of MASTAR on silicon data is shown, as well as prediction of device behaviour due to architectural changes. The generated pre-SPICE parameters are applied to small circuit simulations such as a 10-bit adder, and we show the impact of variability on static random access memory (SRAM) functionality.

Back-end limitations in advanced nodes and alternatives

The back-end scaling is increasing the interconnections parasitic elements. In this paper, we analyze the performance of advanced nodes back-end considering a first order evaluation layout. Parasitic elements are extracted and then SPICE simulations were done using compact models for 14, 10, 7 and 5nm. Finally, we present the simulation of possible candidates to increase BEOL performance, such air-gaps and 3D sequential integration.

Delay partitioning helps reducing variability in 3DVLSI

3DVLSI is an emerging more than Moore technology. In this paper, we propose 3D design methodologies dealing with process variability. Using SPICE models and Monte Carlo simulations we show a delay partioning method for stacked circuits to reduce frequency dispersion by 30%. We also compare how the process correlation between tiers influences the design corners.

Guidelines on 3DVLSI design regarding the intermediate BEOL process influence

This paper aims at identifying the critical parameters for intermediate back end of line (BEOL) in 3DVLSI in order to benefit from higher circuit gain in performance. Thanks to circuit simulations in a 3D environment PDK, the capacitance is identified as the most critical parameter for IC performance of circuits using two intermetal levels. The critical wirelength upon which a gain in performance is obtained by the 3D stacking is evaluated as a function of BEOL flavor.

Test structures for interdie variations monitoring in presence of statistical random variability

We study the limitations of single transistor test structures for Process Variations monitoring in presence of statistical random variability, and compare them with transistor array structures in 45 CMOS technology. By optimizing transistor array design considering statistical variability, layout effects, and interconnect parasitics, we first estimate and then verify on silicon that x5 reduction of statistical variability and excellent correlation with ring oscillator frequency that can be reached for array structure. Transistor arrays are demonstrated to be well suited for monitoring impact of process variations, whether it is die-to-die, or wafer-to-wafer.

A 40nm CMOS 260kb SRAM-bitcell on-chip failure monitoring test scribe with integer-to-current converter

Following the circuit integration trend, the process monitoring structures need to predict the production circuits reliability while keeping test time small and preserving the wafer area. The design presented monitors a 40nm CMOS bitcell failure evolution with supply voltage within a 260kb SRAM matrix and reports the number of fails through an integer-to-current converter. It approximates huge population bitcells reliability while reusing scribe lane test equipment. The design test time is 1s per voltage value; the design height is limited to 60um to fit in sawing region between circuits.