Jean-Michel Portal

Self-consistent physical modeling of set/reset operations in unipolar resistive-switching memories

This Letter deals with a self-consistent physical model for set/reset operations involved in unipolar resistive switching memories integrating a transition metal oxide. In this model, set operation is described in terms of a local electrochemical reduction of the oxide leading to the formation of metallic conductive filaments. Beside, reset operation relies on the thermally assisted destruction of the formed metallic filaments by Joule heating effect. An excellent agreement is demonstrated with numerous published experimental data suggesting that this model can be confidently implemented into circuit simulators for design purpose.

FDSOI Floating Body Cell eDRAM Using Gate-Induced Drain-Leakage (GIDL) Write Current for High Speed and Low Power Applications

A Capacitorless IT-DRAM cell using gate-induced drain leakage (GIDL) current for write operation was demonstrated for the first time on FDSOI substrate, 9.5 nm silicon film and 19 nm BOX. 20 nm gate scaling improves 20% memory effect amplitude. GIDL mechanism allows low bias, low power, fast write time and does not affect intrinsic retention time. A similar value of 10 ms at 85degC is obtained like for impact ionization (II) optimised devices.

Robust Compact Model for Bipolar Oxide-Based Resistive Switching Memories

Emerging nonvolatile memories based on resistive switching mechanisms pull intense research and development efforts from both academia and industry. Oxide-based resistive random access memories (OxRAM) gather noteworthy performances, such as fast WRITE/READ speed, low power, high endurance, and large integration density that outperform conventional flash memories. To fully explore new design concepts, such as distributed memory in logic or biomimetic architectures, robust OxRAM compact models must be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we propose a physics-based compact model used in electrical simulator for bipolar OxRAM memories. After uncovering the theoretical background and the set of relevant physical parameters, this model is confronted to experimental electrical data. The excellent agreement with these data suggests that this model can be confidently implemented into circuit simulators for design purpose.

Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications

Combining Resistive RAM concept with Vertical NAND technology and design, Vertical RRAM (VRRAM) was recently proposed as a cost-effective and extensible technology for future mass data storage applications [1]. 3D RRAM based neural networks were also proposed to emulate the potentiation and depression of a synapse [2], but more complex circuits were not discussed. In previous works [3-4], various RRAM based neuromorphic circuits were proposed and investigated, using planar devices.

Impact of hump effect on MOSFET mismatch in the sub-threshold area for low power analog applications

Analog circuit designs are often biased to work in sub-threshold mode with good gate-source voltage matching performances. Depending on the process, hump effect may change the MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. To model the hump effect, two narrow parasitic MOS are introduced in parallel with the main device. To accurately simulate matching degradation in sub-threshold mode, these parasitic transistors, in case of hump effect, have to be considered.

Compact modeling solutions for OxRAM memories

Emerging non-volatile memories based on resistive switching mechanisms pull intense R&D efforts from both academia and industry. Oxide-based Resistive Random Acces Memories (namely OxRAM) gather noteworthy performances, such as fast write/read speed, low power and high endurance outperforming therefore conventional Flash memories. To fully explore new design concepts such as distributed memory in logic, OxRAM compact models have to be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we present an compact models of the bipolar OxRAM memory based on physical phenomenons. This model was implemented in electrical simulators for single device up to circuit level.

Circuit Effect on Collection Mechanisms Involved in Single Event Phenomena: Application to the Response of a NMOS Transistor in a 90 nm SRAM Cell

SEU is studied in a 90 nm SRAM cell with different simulation approaches. The SRAM cell main SEU parameters (maximum current peak, collected charge, threshold LET) are extracted and compared. It is shown that the simulation conditions have a direct impact on the cell behavior and so on the SEU prediction. Moreover, not accounting for voltage variations induced by the particle generation in the circuit results in an overestimation of struck drain current.

EEPROM Compact Model with SILC Simulation Capability

The objective of this paper is to present a EEPROM compact model suitable for SILC simulation. The SILC module allows simulating the retention capability of the cell after stress. Test chip array distribution and standard tunnel capacitor are used to extract the SILC module parameters. Thus the extraction procedure is detailed. The description of the complete model is presented. A simulation example is given and validated versus measurements.

Test Structure for Process and Product Evaluation

The objective of this paper is to present a test structure introduced in the scribe lines designed to detect process drift and to characterize product performances, i.e. delay and VDDmin. A brief overview of the structure, designed in a ST-Microelectronics 130nm technology, is given. The main advantages of the structure are to be introduced in the scribe line and to have a complex architecture close to the product back-end configurations. A specific test flow is applied to the structure in order to extract relevant data (frequency, delay and bias). The monitoring efficiency of the structure is validated with measurement correlation performed on the structure data, parametric test data and full test chip data.

Vertical CBRAM (V-CBRAM): From Experimental Data to Design Perspectives

In this paper, we propose the integration of an Al2O3/CuTex based Conductive Bridge RAM (CBRAM) device in vertical configuration. The performances of the memory devices are evaluated. 20ns switching time, up to 106 cycles and stable 150°C retention were demonstrated. Functionality is compared with Vertical RRAM integrating an HfO2/Ti OXRAM stack, showing the pros and cons of each configuration. Then 2 potential applications are discussed using design approach. For high density, the Vertical RRAM cell features and circuit are dimensioned to optimize the memory page density. Finally, for neuromorphic applications, selector and array configuration are tuned to reduce the variability in terms of voltage seen by each cell constituting a vertical synapse.