H. Aziza

Impact of hump effect on MOSFET mismatch in the sub-threshold area for low power analog applications

Analog circuit designs are often biased to work in sub-threshold mode with good gate-source voltage matching performances. Depending on the process, hump effect may change the MOS characteristics for negative Bulk-Source Voltage (VBS) and have a slight impact for VBS=0V. To model the hump effect, two narrow parasitic MOS are introduced in parallel with the main device. To accurately simulate matching degradation in sub-threshold mode, these parasitic transistors, in case of hump effect, have to be considered.

An automated methodology to diagnose geometric defect in the EEPROM cell

The objective of this paper is to present an automated geometric defect diagnosis methodology for EEPROM cell (AGDE). This method focuses on speeding up the diagnosis process of geometric defects. It is based on a mathematical model generated with a design of simulation (DOS) technique. The DOS technique takes as input, simulations results of a floating gate transistor with different given geometries and produces, as output, a polynomial equation of the threshold voltage in function of the cells geometric parameters. The diagnosis process is realized by comparing the measured threshold voltages of an EEPROM cell with the dynamically computed ones. From this comparison, the potentially defective geometric parameters are automatically extracted.

Active “multi-fingers”: Test structure to improve MOSFET matching in sub-threshold area

Low power analog applications are often designed under threshold and can be degraded by hump effect. This effect is explained through device dimensions and body bias studies. A MOSFET matching improvement in sub-threshold area is demonstrated with active “multi-fingers” test structure.

Octagonal MOSFET: Reliable device for low power analog applications

Low power analog circuits needs large and short MOSFETs biased in the sub-threshold area with good performances in terms of matching. In order to reach these specifications, octagonal transistors are proposed. Due to their design, these transistors avoid hump effect. As a consequence, gate-source voltage matching under-threshold is always at its best level. Moreover, the paper shows the device robustness to hot carrier stress is improved on octagonal NMOS; VT matching degradation due to hot carrier stress is also improved with an octagonal design.

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress

Device degradation modelling is more and more important for reliable circuit design. On MOSFET, the threshold voltage drift in time can lead to circuit performance degradation. In this study, VT shift due to Hot Carrier Injection stress is accelerated on small width devices. VT matching is also degraded during stress as a function of VT deterioration. This width dependence allows explaining gate voltage matching behavior in the sub-threshold area used in low power analog applications.

An efficient model to evaluate the impact of design parameters on charge pump circuits’ performances: Application on RFID circuits

In this paper a charge pump model based on a DOE (design of experiment) model generation technique is presented. The DOE technique takes as input electrical simulation results of a charge pump circuit for different component geometries and different oscillator pulse periods. It produces, as outputs, polynomial equations of the charge pump output voltage HV and the consumption current ISUNK. Using those equations, impact of specific charge pump design parameters on charge pump outputs is clearly shown. Thus, design guidelines can be followed to optimize charge pump circuits efficiency. To validate this approach, this optimization methodology is used to evaluate the charge pump optimal configuration of a low voltage and low current IC circuit (RFID tag).

Speeding up simulation time in EEPROM memory designs

This paper presents an efficient technique to decrease simulation lime of EEPROM memory arrays. This technique is based on the complexity reduction of an existing compact EEPROM model. This original model is unsuitable when dealing with large memory arrays simulations. To overcome this limitation, the authors propose two alternative models which allow reducing time and memory space overheads when compared to the compact model. The first EEPROM model (level 1). is as simple as possible and provides fast simulation time. The second model (level 2) is a compromise between the compact model and the level 1 model. We also present simulation time results using these different models within memory arrays

Non volatile memory reliability prediction based on oxide defect generation rate during stress and retention tests

This paper shows how Floating Gate (FG) memory cells behavior during retention tests can be predicted relying on static electrical stress tests. Retention tests are usually performed at High or Low Temperature Bake (HTB or LTB respectively) to provide warning of an impending failure of the memory cell capability to store data. Retention tests are very useful to screen out defective cell populations but induce significant test time overhead. To overcome this limitation, a correlation between stress and retention time is established to anticipate retention test results. Moreover, further investigations are made to provide a physical explanation for the correlation. Indeed, it is shown that the same FG memory tunnel oxide traps are activated during electrical stress tests (high electric field) and retention tests (low electric field).

Investigation of EEPROM memories reliability during endurance and retention tests

To ensure reliability of EEPROM devices, it is significant to monitor the evolution of the memory array threshold voltage (VT) distribution. In this work, impact of endurance and retention tests is evaluated on EEPROM VT distributions. To track accurately the evolution of the VT distribution, an innovative experimental plan is setup and experimental results are deeply analyzed.

Peripheral Circuitry Impact on LEPROM Threshold Voltage

The fundamental discussion of this paper is to show the influence of peripheral circuits marginalities, like reading and programming circuitry, on the threshold voltage (Vth) distributions of an EEPROM memory array. The initial Vth dispersion induced by peripheral circuits is tracked during cycling/retention test. To understand Vth distribution variation within the memory array, simulations are performed using an elementary circuit composed of 128 memory cells. Experimental results are given for an ST-Microelectronics 512 Kbits EEPROM test vehicle.