Didier Née
STMicroelectronics
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Publication
Featured researches published by Didier Née.
Journal of Electronic Testing | 2005
Jean Michel Portal; Hassen Aziza; Didier Née
Knowing, that the threshold voltage of the EEPROM memory cells is a key parameter to determine the overall performance of the memory, a built in structure to extract this information is a very relevant choice to fast diagnose the failure in the memory. Thus, the objective of this paper is to present a built in self-diagnosis of EEPROM memory cells, based on threshold voltage extraction. In order to extract the threshold voltage, the modified circuit and the associated test sequence are presented. Based on the threshold voltage extraction, complementary information is proposed to improve the classical memory diagnosis methodology.
international conference on microelectronic test structures | 2007
F. Rigaud; Jean-Michel Portal; H. Aziza; Didier Née; J. Vast; C. Auricchio; Bertrand Borot
The objective of this paper is to present a test structure introduced in the scribe lines designed to detect process drift and to characterize product performances, i.e. delay and VDDmin. A brief overview of the structure, designed in a ST-Microelectronics 130nm technology, is given. The main advantages of the structure are to be introduced in the scribe line and to have a complex architecture close to the product back-end configurations. A specific test flow is applied to the structure in order to extract relevant data (frequency, delay and bias). The monitoring efficiency of the structure is validated with measurement correlation performed on the structure data, parametric test data and full test chip data.
design, automation, and test in europe | 2005
Laurent Lopez; Jean Michel Portal; Didier Née
The embedded DRAM (eDRAM) is more and more used in system-on-chip (SOC). It is challenging to integrate the DRAM capacitor process into a logic process to get satisfactory yields. The specific process of DRAM capacitor and the low capacitance value (/spl sim/30 fF) of this device induce problems of process monitoring and failure analysis. We propose a new test structure to measure the capacitance value of each DRAM cell capacitor in a DRAM array. This concept has been validated by simulation on a 0.18 /spl mu/m eDRAM technology.
international symposium on circuits and systems | 2002
Jean Michel Portal; L. Forli; Didier Née
international test conference | 2002
Jean Michel Portal; L. Forli; H. Aziza; Didier Née
international conference on microelectronic test structures | 2008
F. Rigaud; Jean-Michel Portal; H. Aziza; Didier Née; J. Vast; Fabrice Argoud; Bertrand Borot
memory technology design and testing | 2002
Jean Michel Portal; L. Forli; H. Aziza; Didier Née
Microelectronics Reliability | 2011
Fabrice Rigaud; Jean Michel Portal; Hassen Aziza; Didier Née; Julien Vast; Fabrice Argoud; Bertrand Borot
defect and fault tolerance in vlsi and nanotechnology systems | 2005
B. Saillet; Jean Michel Portal; Didier Née
international symposium on circuits and systems | 2002
Jean Michel Portal; L. Forli; Didier Née