Bertrand Le-Gratiet

Toward 7nm target on product overlay for C028 FDSOI technology

The continuous need for lithography overlay performance improvement is a key point for advanced integrated circuit manufacturing. Overlay control is more and more challenging in the 2x nm process nodes regarding functionality margin of the chip and tool capability. Transistor architecture rules which are set, confirm poly to contact space as the most critical one for 28nm technology node. Critical Dimension variability of these layers, even with best in class process stability, in addition to design constraint lead to on product overlay specifications of around 7nm. In order to ensure that the target is met in production environment and to identify potential ways for improvement, identification of the contributors to overlay errors is essential. We have introduced a novel budget breakdown methodology using both bottom-up and top-down overlay data. For the bottom up part, we have performed extensive testing with very high sampling scheme so as to quantify the main effects. In-line overlay metrology data has been used for top down approach to verify the overall performance in production. In this paper we focused on the 28nm contact to gate overlay in a FDSOI process. The initial inconsistency between bottom up and top down results led us to further exploration of the root cause of these inconsistencies. We have been able to highlight key figures to focus on, like reticle heating, wafer table contamination and etch processing effects. Finally, we conclude on 7nm overlay target achievement feasibility in high volume manufacturing environment.

Verification and application of multi-source focus quantification

The concept of the multi-source focus correlation method was presented in 2015 [1, 2]. A more accurate understanding of real on-product focus can be obtained by gathering information from different sectors: design, scanner short loop monitoring, scanner leveling, on-product focus and topography. This work will show that chip topography can be predicted from reticle density and perimeter density data, including experimental proof. Different pixel sizes are used to perform the correlation in-line with the minimum resolution, correlation length of CMP effects and the spot size of the scanner level sensor. Potential applications of the topography determination will be evaluated, including optimizing scanner leveling by ignoring non-critical parts of the field, and without the need for time-consuming offline topography measurements.

Process window optimizer for pattern based defect prediction on 28nm metal layer

At the 28nm technology node and below, hot spot prediction and process window control across production wafers have become increasingly critical. We establish proof off concept for ASML’s holistic lithography hot spot detection and defect monitoring flow, process window optimizer (PPWO), for a 228nm metal layer process. We demonstrate prediction and verification of defect occurrence on wafer that arise from focus variations exceeding process window margins of device hotspots. We also estimate the improvement potential if design aware scanner control was applied.

Predictability and impact of product layout induced topology on across-field focus control

With continuing dimension shrinkage using the TWINSCAN NXT:1950i scanner on the 28nm node and beyond, the imaging depth of focus (DOF) becomes more critical. Focus budget breakdown studies [Ref 1, 5] show that even though the intrafield component stays the same this becomes a larger relative percentage of the overall DOF. Process induced topography along with reduced Process Window can lead to yield limitations and defectivity issues on the wafer. To improve focus margin, a study has been started to determine if some correlations between scanner levelling performance, product layout and topography can be observed. Both topography and levelling intrafield fingerprints show a large systematic component that seems to be product related. In particular, scanner levelling measurement maps present a lot of similarities with the layout of the product. The present paper investigates the possibility to model the level sensor’s measured height as a function of layer design densities or perimeter data of the product. As one component of the systematics from the level sensor measurements is process induced topography due to previous deposition, etching and CMP, several layer density parameters were extracted from the GDS’s. These were combined through a multiple variable analysis (PLS: Partial Least Square regression) to determine the weighting of each layer and each parameter. Current work shows very promising results using this methodology, with description quality up to 0.8 R2 and expected prediction quality up to 0.78 Q2. Since product layout drives some intrafield focus component it is also important to be able to assess intrafield focus uniformity from post processing. This has been done through a hyper dense focus map experiment which is presented in this paper.

Patterning critical dimension control for advanced logic nodes

Abstract. Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.

Product layout induced topography effects on intrafield levelling

With continuing dimension shrinkage using the TWINSCAN NXT:1950i scanner on the 28nm node and beyond, the imaging depth of focus (DOF) becomes more critical. Focus budget breakdown studies [Ref 2, 5] show that even though the intrafield component stays the same, it becomes a larger relative percentage of the overall DOF. Process induced topography along with reduced Process Window can lead to yield limitations and defectivity issues on the wafer. In a previous paper, the feasibility of anticipating the scanner levelling measurements (Level Sensor, Agile and Topography) has been shown [1]. This model, built using a multiple variable analysis (PLS: Partial Least Square regression) and GDS densities at different layers showed prediction capabilities of the scanner topography readings up to 0.78 Q² (the equivalent of R² for expected prediction). Using this model, care areas can be defined as parts of the field that cannot be seen nor corrected by the scanner, which can lead to local DOF shrinkage and printing issues. This paper will investigate the link between the care areas and the intrafield focus that can be seen at the wafer level, using offline topography measurements as a reference. Some improvements made on the model are also presented.

Effect of etch pattern transfer on local overlay (OVL) margin in 28nm gate integration.

One of the main process control challenges in logic process integration is the contact to gate overlay. Usual ways for overlay control are run to run corrections (high order process corrections) and scanner control (baseliner control loop) to keep overlay within the very tight ITRS specifications, i.e. 7nm mean+3sigma. It is known that process integration can lead to specific overlay distortion (CMP, thermal treatment etc…) which are usually partly handled by high order process corrections at scanner level. In addition, recently we have shown that etch process can also lead to local overlay distortions, especially at the wafer edge [1]. In this paper we look into another overlay distortion level which can happen during etch processes. We will show that resist cure steps during gate patterning affect lithography defined profiles leading to local pattern shifting. This so called gate shifting has been characterized by etch process partitioning during a typical high-K metal gate patterning with spinon carbon and Si-ARC lithography stack onto a high-K metal gate / poly-silicon / oxide hard mask stack. We will show that modifying the resist-cure / Si-ARC open chemistry strongly contributes to gate shifting reduction by an equivalent of 40% overlay margin reduction.

Improving lithography intra wafer CD for C045 implant layers using STI thickness feed forward

In this paper we performed an analysis of various data collection preformed on C045 production lots in order to assess the influence of STI oxide layers on the CD uniformity of implant photolithography layers. Our final purpose is to show whether the DOSE MAPPERTM software option for interfiled dose correction available on ASML scanners combined with a run-to-run feed-forward regulation loop could improve global CD uniformity on C045 implants layers. After a brief presentation of the C045 implants context the results of the analysis are presented : swing curves, process windows analysis, and intra-die CD measurements are presented. The conclusion of the analysis is that it is not possible, in the current C045 industrial environment, to use a robust and general method of interfield dose correction in order to achieve a better global CD uniformity.

SEM contour based metrology for microlens process studies in CMOS image sensor technologies

From the first digital cameras which appeared during the 70s to cameras of current smartphones, image sensors have undergone significant technological development in the last decades. The development of CMOS image sensor technologies in the 90s has been the main driver of the recent progresses. The main component of an image sensor is the pixel. A pixel contains a photodiode connected to transistors but only the photodiode area is light sensitive. This results in a significant loss of efficiency. To solve this issue, microlenses are used to focus the incident light on the photodiode. A microlens array is made out of a transparent material and has a spherical cap shape. To obtain this spherical shape, a lithography process is performed to generate resist blocks which are then annealed above their glass transition temperature (reflow). Even if the dimensions to consider are higher than in advanced IC nodes, microlenses are sensitive to process variability during lithography and reflow. A good control of the microlens dimensions is key to optimize the process and thus the performance of the final product. The purpose of this paper is to apply SEM contour metrology [1, 2, 3, 4] to microlenses in order to develop a relevant monitoring methodology and to propose new metrics to engineers to evaluate their process or optimize the design of the microlens arrays.

Microlens under melt in-line monitoring based on application of neural network automatic defect classification

The usage of convolutional neural networks (CNN) on images is spreading into various topics in lot of industries. Today in the semiconductor industry CNN are used to perform Automatic Defect Classification (ADC) on SEM review images in almost real time and with level of success as high as trained operators can do or more [1,2]. The possibilities to get new kind of information from images offer to engineers multiple potential usages. In this paper we propose to present derivatives usages of CNN applied to the CD-SEM metrology with specific focus on an application to detect undermelted microlens in our imager process flow [3]. CD-SEM metrology is used to perform Critical Dimension (CD) measurement on almost all patterning steps in the wafer cycle (after lithography and after etch). CNN allows us to get more information from pictures than only dimensions measured by the CD-SEM used to feed a control card. In our imager process flow we have steps to form microlenses. The microlens process fabrication consists in a first lithography step where microlens matrix is defined in resist. The result is a matrix of quite square parallelepipoid microlenses followed by a melting step in order to reflow resists and eventually form microlens with spherical cap shape. The figure 1 shows the evolution of microlens shape in function of melting process time.