Bastien Orlando

DAPHNE silicon photonics technological platform for research and development on WDM applications

A new technological platform aimed at making prototypes and feasibility studies has been setup at STMicroelectronics using 300mm wafer foundry facilities. The technology, called DAPHNE (Datacom Advanced PHotonic Nanoscale Environment), is devoted at developing and evaluating new devices and sub-systems in particular for wavelength division multiplexing (WDM) applications and ring resonator based applications. Developed in the course of PLAT4MFP7 European project, DAPHNE is a flexible platform that fits perfectly R&D needs. The fabrication flow enables the processing of photonic integrated circuits using a silicon-on-insulator (SOI) of 300nm, partial etches of 150nm and 50nm and a total silicon etching. Consequently, two varieties of rib waveguides and one strip waveguide can be fabricated simultaneously with auto-alignment properties. The process variability on the 150nm partially etched silicon and the thin 50nm slab region are both less than 6 nm. Using a variety of different implantation configurations and a back-end of line of 5 metal layers, active devices are fabricated both in germanium and silicon. An available far back-end of line process consists of making 20 μm diameter copper posts on top of the electrical pads so that an electronic integrated circuit can be bonded on top the photonic die by 3D integration. Besides having those fabrication process options, DAPHNE is equipped with a library of standard cells for optical routing and multiplexing. Moreover, typical Mach-Zehnder modulators based on silicon pn junctions are also available for optical signal modulation. To achieve signal detection, germanium photodetectors also exist as standard cells. The measured single-mode propagation losses are 3.5 dB/cm for strip, 3.7 dB/cm for deep-rib (50nm slab) and 1.4 dB/cm for standard rib (150nm slab) waveguides. Transition tapers between different waveguide structures are as low as 0.006 dB.

Patterning critical dimension control for advanced logic nodes

Abstract. Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.

Improving lithography intra wafer CD for C045 implant layers using STI thickness feed forward

In this paper we performed an analysis of various data collection preformed on C045 production lots in order to assess the influence of STI oxide layers on the CD uniformity of implant photolithography layers. Our final purpose is to show whether the DOSE MAPPERTM software option for interfiled dose correction available on ASML scanners combined with a run-to-run feed-forward regulation loop could improve global CD uniformity on C045 implants layers. After a brief presentation of the C045 implants context the results of the analysis are presented : swing curves, process windows analysis, and intra-die CD measurements are presented. The conclusion of the analysis is that it is not possible, in the current C045 industrial environment, to use a robust and general method of interfield dose correction in order to achieve a better global CD uniformity.

Si-photonics waveguides manufacturability using advanced RET solutions

Si-Photonics is the technology in which data is transferred by photons (i. e. light). On a Photonic Integrated Circuit (PIC), light is processed and routed on a chip by means of optical waveguides. The Si-Photonics waveguides functionality is determined by its geometrical design which is commonly curved, skew and non-Manhattan. That is why printing fidelity is very challenging on photonics patterns. In this paper, we present two different Optical Proximity Correction (OPC) flows for Si-Photonics patterning. The first flow is regular model based OPC and the second one is based on Inverse Lithography Technology (ILT). The first OPC flow needs first to retarget the input layout while the ILT flow does support skew edges input by tool design and does not need any retargeting step before OPC. We will compare these two flows on various Si- Photonics waveguides from lithography quality, run time and MRC compliance of mask output. We will observe that ILT flow gives the best Edge Placement Error (EPE) and the lowest ripples along the devices. The ILT flow also takes into account the mask rules so that the generated mask is mask rule compliant (MRC). We will also discuss the silicon wafer data where Si-Photonics devices are printed within the two different OPC flows at process window conditions. Finally, for both OPC flows, we will present the total OPC run time which is acceptable in an industrial environment.

OPC for curved designs in application to photonics on silicon

Todays design for photonics devices on silicon relies on non-Manhattan features such as curves and a wide variety of angles with minimum feature size below 100nm. Industrial manufacturing of such devices requires optimized process window with 193nm lithography. Therefore, Resolution Enhancement Techniques (RET) that are commonly used for CMOS manufacturing are required. However, most RET algorithms are based on Manhattan fragmentation (0°, 45° and 90°) which can generate large CD dispersion on masks for photonic designs. Industrial implementation of RET solutions to photonic designs is challenging as most currently available OPC tools are CMOS-oriented. Discrepancy from design to final results induced by RET techniques can lead to lower photonic device performance. We propose a novel sizing algorithm allowing adjustment of design edge fragments while preserving the topology of the original structures. The results of the algorithm implementation in the rule based sizing, SRAF placement and model based correction will be discussed in this paper. Corrections based on this novel algorithm were applied and characterized on real photonics devices. The obtained results demonstrate the validity of the proposed correction method integrated in Inscale software of Aselta Nanographics.

How holistic process control translates into high mix logic fab APC

Advanced CMOS nodes require more and more information to get the wafer process well setup. Process tool intrinsic capabilities are not sufficient to secure specifications. APC systems (Advanced Process Control) are being developed in waferfab to manage process context information to automatically adjust and tune wafer processing. The APC manages today Run to Run component from and between various process steps plus a sub-recipes/profiles corrections management. This paper will outline the architecture of an integrated/holistic process control system for a high mix advanced logic waferfoundry.

Overlay improvement through lot-based feed-forward: applications to various 28nm node lithography operations

We introduced a very simple overlay feed forward correction based on lot data issued from previous lithography operations. Simple method for correction factor optimization was also proposed. We applied this method in various cases based on 28nm node early production: implants lithography on 248nm tools, contact holes double patterning on 193nm immersion tool, and we also tried to improve contact holes patterning based on 248nm lithography data. All analysis were based on early production 28nm node data mixing 28LP and 28FDSOI technologies. We first optimized the correction based on our simple approach, and then compute the dispersion of all linear overlay parameters. Maximum modeled overlay error was also computed. In most cases we obtained significant improvements. The interest of such a very simple approach that requires reduced software development and allows simple implementation was thus demonstrated.

Scatterometry-based dose and focus decorrelation: applications to 28nm contact holes patterning intrafield focus investigations

We introduced a simple method based on scatterometry measurement performed on dense contact holes matrix to investigate intrafield focus deviation on 28nm FDSOI real production wafers at contact holes patterning lithography operation. A complex three-dimensional scatterometry model with all patterned resist geometrical parameters left as degree of freedom. Then simple linear relationships between patterned resist geometrical parameters on the one hand, and applied dose and focus offset on the other hand were used to determine a focus and dose decorrelation model. This model was then used to investigate the effect of ASML AGILETM scanner option on intrafield focus deviation. A significant 16% intrafield focus standard deviation improvement was found with AGILETM, which validated our method and shows the possibilities of AGILETM option for intrafield focus control. This focus investigation method may be used to improve advanced CMOS manufacturing process control.