Maxime Gatefait

Overlay breakdown methodology on immersion scanner

In the last years a flourishing number of techniques such as High Order Control or mappers have been proposed to improve overlay control. However a sustainable improvement requires sometimes understanding the underlying causes of the overlay limiting factors in order to remove them when possible or at least to keep them under control. Root cause finding for overlay error is a tough task due the very high number of influencing parameters and the interaction of the usage conditions. This paper presents a breakdown methodology to deal with this complexity and to find the contributors of overlay error variation. We use a Partial Least Squares (PLS) algorithm to isolate the key contributors for correctable terms and a field-to-field linear regression technique to highlight the main causes of residuals. We present a study carried out on 45nm CMOS contact-gate overlay over 687 production wafers exposed in an ASML TWINSCAN XT:1700i Immersion scanner. We present the results of the correlations with the 180 process and equipment variables used for this study. For each isolated contributor we propose an explanation of the underlying physical phenomenon and solutions.

Process Control for 45 nm CMOS logic gate patterning

This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer, intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay performance with immersion lithography is also presented.

Pattern recognition and data mining techniques to identify factors in wafer processing and control determining overlay error

On-product overlay can be improved through the use of context data from the fab and the scanner. Continuous improvements in lithography and processing performance over the past years have resulted in consequent overlay performance improvement for critical layers. Identification of the remaining factors causing systematic disturbances and inefficiencies will further reduce overlay. By building a context database, mappings between context, fingerprints and alignment & overlay metrology can be learned through techniques from pattern recognition and data mining. We relate structure (‘patterns’) in the metrology data to relevant contextual factors. Once understood, these factors could be moved to the known effects (e.g. the presence of systematic fingerprints from reticle writing error or lens and reticle heating). Hence, we build up a knowledge base of known effects based on data. Outcomes from such an integral (‘holistic’) approach to lithography data analysis may be exploited in a model-based predictive overlay controller that combines feedback and feedforward control [1]. Hence, the available measurements from scanner, fab and metrology equipment are combined to reveal opportunities for further overlay improvement which would otherwise go unnoticed.

Toward 7nm target on product overlay for C028 FDSOI technology

The continuous need for lithography overlay performance improvement is a key point for advanced integrated circuit manufacturing. Overlay control is more and more challenging in the 2x nm process nodes regarding functionality margin of the chip and tool capability. Transistor architecture rules which are set, confirm poly to contact space as the most critical one for 28nm technology node. Critical Dimension variability of these layers, even with best in class process stability, in addition to design constraint lead to on product overlay specifications of around 7nm. In order to ensure that the target is met in production environment and to identify potential ways for improvement, identification of the contributors to overlay errors is essential. We have introduced a novel budget breakdown methodology using both bottom-up and top-down overlay data. For the bottom up part, we have performed extensive testing with very high sampling scheme so as to quantify the main effects. In-line overlay metrology data has been used for top down approach to verify the overall performance in production. In this paper we focused on the 28nm contact to gate overlay in a FDSOI process. The initial inconsistency between bottom up and top down results led us to further exploration of the root cause of these inconsistencies. We have been able to highlight key figures to focus on, like reticle heating, wafer table contamination and etch processing effects. Finally, we conclude on 7nm overlay target achievement feasibility in high volume manufacturing environment.

Patterning critical dimension control for advanced logic nodes

Abstract. Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.

Improving lithography intra wafer CD for C045 implant layers using STI thickness feed forward

In this paper we performed an analysis of various data collection preformed on C045 production lots in order to assess the influence of STI oxide layers on the CD uniformity of implant photolithography layers. Our final purpose is to show whether the DOSE MAPPERTM software option for interfiled dose correction available on ASML scanners combined with a run-to-run feed-forward regulation loop could improve global CD uniformity on C045 implants layers. After a brief presentation of the C045 implants context the results of the analysis are presented : swing curves, process windows analysis, and intra-die CD measurements are presented. The conclusion of the analysis is that it is not possible, in the current C045 industrial environment, to use a robust and general method of interfield dose correction in order to achieve a better global CD uniformity.

Industrial characterization of scatterometry for advanced APC of 65 nm CMOS logic gate patterning

CMOS 65nm technology node requires the introduction of advanced materials for critical patterning operations. The study is focused on the multilayer Anti Reflective Coating (ARC) stack, used in photolithography, for the gate patterning such as Advanced Patterning Film (APF). The interest on this new and complex ARC stack lies in the benefit to guarantee low CD dispersion thanks to a better reflectivity control and resist budget which leads to a larger lithographic process window. However, it implies numerous metrology challenges. The paper deals with the challenges of monitoring the gate Critical Dimension (CD) on this stack. The validation of the scatterometry model versus stack thicknesses and indexes variations, through experiments, is also described. The final result is the complete characterization of the materials for thickness and scatterometry CD control, for photo feedback and for etch feed-forward deployment in an industrial mode. The analysis shows that scatterometry measurements on a standard 65 nm gate process ensure a better effectiveness than the CD Scanning Electron Microscopy (SEM) ones when injected in the Advanced Process Control (APC) system from photo to etch.

Approaches of multilayer overlay process control for 28nm FD-SOI derivative applications

Derivative technology like embedded Non-Volatile Memories (eNVM) is raising new types of challenges on the “more than Moore” path. By its construction: overlay is critical across multiple layers, by its running mode: usage of high voltage are stressing leakages and breakdown, and finally with its targeted market: Automotive, Industry automation, secure transactions… which are all requesting high device reliability (typically below 1ppm level). As a consequence, overlay specifications are tights, not only between one layer and its reference, but also among the critical layers sharing the same reference. This work describes a broad picture of the key points for multilayer overlay process control in the case of a 28nm FD-SOI technology and its derivative flows. First, the alignment trees of the different flow options have been optimized using a realistic process assumptions calculation for indirect overlay. Then, in the case of a complex alignment tree involving heterogeneous scanner toolset, criticality of tool matching between reference layer and critical layers of the flow has been highlighted. Improving the APC control loops of these multilayer dependencies has been studied with simulations of feed-forward as well as implementing new rework algorithm based on multi-measures. Finally, the management of these measurement steps raises some issues for inline support and using calculations or “virtual overlay” could help to gain some tool capability. A first step towards multilayer overlay process control has been taken.

An evaluation of edge roll off on 28nm FDSOI (fully depleted silicon on insulator) product

On product wafers, scanner focus is better controlled at the wafer center than at the wafer edge. This is due, in a large part, to edge roll off effects [1]. This paper quantifies the impact of edge roll off on scanner levelling non-correctable errors and correlates this to on-product effects. The main contributors and mitigation methods are also discussed for a NXT:1950 scanner.

Higher order feed-forward control of reticle writing error fingerprints

The understanding and control of the intra-field overlay budget becomes crucial particularly after the introduction of multi-patterning applications. The intra-field overlay budget is built-up out of many contributors, each with its own characteristic. Some of them are (semi-)static like the reticle writing error (RWE) fingerprint, the scanner lens fingerprint, or the intra-field processing signature. Others are more dynamic. Examples are reticle heating and lens heating due to the absorption of a small portion of the exposure light. Ideally, all overlay contributors that are understood and known could be taken out of the feed-back control loop and send as feed-forward corrections to the scanner. As a consequence, only non-correctable overlay residuals are measured on the wafer. In the current work, we have studied the possibility to characterize the reticle writing error fingerprint by an off-line position measurement tool and use this information to send feed-forward corrections to the ASML TWINSCANTM exposure tool. The current work is an extension of the work we published earlier. To this end, we have selected a reticle pair out of 50 production reticles that are used to manufacture a 28-nm technology device. These two reticles are special in the sense that the delta fingerprint contains a significant higher order RWE signature. While previously only the linear parameters were sent as feed-forward corrections to the ASML TWINSCANTM exposure tool, this time we additionally demonstrate the capability to correct for the non-linear terms as well. Since the concept heavily relies on the quality of the off-line mask registration measurements, a state-of-the-art reticle registration tool was chosen. Special care was taken to eliminate any effects of the tool induced shifts that may affect the quality of the measurements. The on-wafer overlay verification measurements were performed on an ASML YieldStar metrology tool as well as on a different vendor tool. In conclusion, we have extended and proven the concept of using off-line reticle registration measurements to enable higher order feed-forward corrections the ASML TWINSCANTM scanner. This capability has been verified by on-wafer overlay measurements. It is demonstrated that the RWE contribution in the overlay budget can be taken out of the feedback control loop and sent as feed-forward corrections instead. This concept can easily be extended when more scanner corrections become available.