Bing Xie

High-Performance Normally-Off

This letter reports a normally-OFF Al₂O₃/GaN gate-recessed MOSFET using a low-damage digital recess technique featuring multiple cycles of plasma oxidation and wet oxide removal process. The wet etching process eliminates the damage induced by plasma bombardment induced in conventional inductively coupled plasma dry etching process so that good surface morphology and high interface quality could be achieved. The fully recessed Al₂O₃/GaN MOSFET delivers true enhancement-mode operation with a threshold voltage of +1.7 V. The maximum output current density is 528 mA/mm at a positive gate bias of 8 V. A peak field-effect mobility of 251 cm²/V·s is obtained, indicating high-quality Al₂O₃/GaN interface.

{\rm Al}_{2}{\rm O}_{3}/{\rm GaN}

A self-terminating gate recess etching technique is first proposed to fabricate normally off AlGaN/GaN MOSFET. The gate recess process includes a thermal oxidation of the AlGaN barrier layer for 40 min at 615°C followed by 45-min etching in potassium hydroxide solution at 70°C, which is found to be self-terminated at the AlGaN/GaN interface with negligible effect on the underlying GaN layer, manifesting itself easy to control, highly repeatable, and promising for industrialization. The fabricated device based on this technique with atomic layer deposition Al2O3 as gate insulator exhibits a threshold voltage as high as 3.2 V with a maximum drain current over 200 mA/mm and a 60% increased breakdown voltage than that of the conventional high electron mobility transistors.

MOSFET Using a Wet Etching-Based Gate Recess Technique

In this paper, we report the device performance of a high-voltage normally off Al₂O₃/GaN MOSFET on the Si substrate. Normally off operation is obtained by multiple cycles of O₂ plasma oxidation and wet oxide-removal gate recess process. The recessed normally off GaN MOSFET with 3 μm gate-drain distance exhibits a maximum drain current of 585 mA/mm at 9 V gate bias. The threshold voltage of the MOSFET is 2.8 V with a standard derivation of 0.2 V on the sample with an area of 2 × 2 cm². The gate leakage current is below 10^-6 mA/mm during the whole gate swing up to 9 V and the ION/IOFF ratio is larger than 109, indicating the good quality of Al₂O₃ gate insulator. The MOSFET with 10 μm gate-drain distance shows a three terminal OFF-state breakdown voltage (BV) of 967 V at zero gate-source bias with a drain leakage current criterion of 1 μA/mm. The specific ON-resistance (R_ON,SP) of the device is 1.6 mQ · cm² and the power figure of merit (BV²/R_ON,SP) is 584 MW/cm².

Fabrication of Normally Off AlGaN/GaN MOSFET Using a Self-Terminating Gate Recess Etching Technique

In this letter, we investigated the behaviors of surface- and buffer-induced current collapse in AlGaN/GaN high-electron mobility transistors (HEMTs) using a soft-switched pulsed I-V measurement with different quiescent bias points. It is found that the surface- and buffer-related current collapse have different relationship with the gate and drain biases (VGS0,VDS0) during quiescent bias stress. The surface-induced current collapse in devices without passivation monotonically increases with the negative VGS0, suggesting that an electron injection to the surface from gate leakage is the dominant mechanism and the Si3N4 passivation could effectively eliminate such current collapse. The buffer-induced current collapse in devices with intentionally carbon-doped buffer layer exhibits a different relationship with VGS0 after surface passivation. The buffer-related current collapse shows a bell-shaped behavior with VGS0, suggesting that a hot electron trapping in the buffer is the dominant mechanism. The soft-switched pulsed I-V measurement provides an effective method to distinguish between the surface- and buffer-related current collapse in group III-nitride HEMTs.

900 V/1.6

In this letter, a plasma-free etch stop structure is developed for GaN HEMT toward enhancement-mode operation. The self-terminated precision gate recess is realized by inserting a thin AlN/GaN bilayer in the AlGaN barrier layer. The gate recess is stopped automatically at the GaN insertion layer after high-temperature oxidation and wet etch, leaving a thin AlGaN barrier to maintain a quantum well channel that is normally pinched off. With addition of an Al2O3 gate dielectric, quasi normally OFF GaN MOSHEMTs have been fabricated with high threshold uniformity and low ON-resistance comparable with the normally ON devices on the same wafer. A high channel mobility of 1400 cm2/V·s was obtained due to the preservation of the high electron mobility in the quantum-well channel under the gate.

{\rm m}\Omega\cdot{\rm cm}^{2}

In this article, a detailed analysis of the wet-etching technique for AlGaN/GaN heterostructure using dry thermal oxidation followed by a wet alkali etching was performed. The experimental results show that the oxidation plays a key role in the wet-etching method and the etching depth is mainly determined by the oxidation temperature and time. The correlation of etching roughness with oxidation time and temperature was investigated. It is found that there exists a critical oxidation temperature in the oxidation process. Finally, a physical explanation of the oxidation procedure for AlGaN layer was given.

Normally Off

Based on our proposed self-terminating gate recess etching technique, normally-off recess-gated AlGaN/GaN MOSFET has been demonstrated with a novel method using GaN cap layer (CL) as recess mask, which, as a result, simplifies the device fabrication process and lowers the fabrication cost. The GaN CL is capable of acting as an effective recess mask for the gate recess process, which includes a thermal oxidation for 45 min at 650 °C followed by 4-min etching in potassium hydroxide (KOH) at 70°C. After gate recess process, no obvious change is observed in terms of the surface morphology of the GaN CL, the contact resistance of the Ohmic contact formed directly on the GaN CL as well as the sheet resistance of the two-dimensional electron gas (2-DEG) channel layer under the GaN CL. The fabricated device exhibits a threshold voltage (Vth) as high as 5 V, a maximum drain current (Idmax) of ~200 mA/mm, a high ON/OFF current ratio of ~1010 together with a low forward gate leakage current of ~10-5 mA/mm. Meanwhile, the OFF-state breakdown voltage (Vbr) of the device with gate-drain distance of 6 μm is 450 V.

{\rm Al}_{2}{\rm O}_{3}/{\rm GaN}

Threshold voltage drift under gate bias stress was investigated in gate-recessed enhancement mode (E-mode) GaN MOSFET and depletion mode (D-mode) GaN MOS high-electron-mobility transistor (MOSHEMT) with Al2O3 gate dielectric layer. Besides the positive shift of threshold voltage in both devices under positive gate stress, it is also found that positive shift could also exist in E-mode GaN MOSFET under negative gate bias stress, while negative shift is observed in D-mode MOSHEMT. A three-step trapping and detrapping process was observed in the drain current transient of the device after negative gate bias stress. It was suggested that gate electron injection and the following trapping in the damaged gate recessed GaN channel layer is the dominant mechanism for the positive shift of the threshold voltage under negative gate bias in the enhancement mode GaN MOSFET.

MOSFET on Silicon Substrate

Postgate annealing (PGA) in N2/O2 atmosphere at 300°C for various annealing time is performed on enhancement mode AlGaN/GaN MOSFET fabricated using a self-terminating gate recess etching technique. After 45-min annealing, the device OFF-state leakage current decreases by more than two orders of magnitude and thus a low OFF-state leakage current of 10-13 A/mm is obtained at room temperature, resulting in an excellent ON/OFF current ratio of ~1012. At 250°C, the device still exhibits a low OFF-state leakage current of ~10-9 A/mm and high ON/OFF current ratio of ~108. Meanwhile, a strong correlation between the OFF-state leakage current and mesa isolation current is observed as we change the annealing time: 1) the lower the mesa isolation current and 2) the lower the OFFstate leakage current and thus the higher the ON/OFF current ratio. It is the suppression of the mesa isolation current owing to the passivation of atomic layer deposition Al2O3 that leads to the improvement of the OFF-state leakage current and ON/OFF current ratio after PGA. Besides, the device shows no obvious change in terms of its threshold voltage and maximum drain current after PGA.

Investigation of Surface- and Buffer-Induced Current Collapse in GaN High-Electron Mobility Transistors Using a Soft Switched Pulsed \(I-V\) Measurement

The temperature dependence of current collapse (CC) in AlGaN/GaN high-electron mobility transistors on silicon substrate is studied in this paper. Devices without and with Si3N4 passivation are used to investigate the behavior of surface- and buffer-induced CC, respectively. It is found that the degree of surface-induced CC in unpassivated devices has a weak temperature dependence, which is induced by the cancelling out between enhanced carrier injection based on surface hopping and enhanced emission when the temperature is increased. On the other hand, the degree of buffer-induced CC in the Si3N4 passivated devices is reduced at higher temperature since the energy of hot electrons is reduced due to the phonon scattering and the trapping of hot electrons in the buffer is mitigated. Temperature-dependent transient measurement is also carried out to investigate the recovery process for these two type of CC. Two types of trap levels are identified in the unpassivated and Si3N4 passivated devices, respectively. The trap level E1 with an activation energy of 0.08 eV is supposed to be related to the surface trapping, while E2 with an activation energy of 0.22 eV is located in the buffer layer.