Min Yu

Analysis of surface roughness in Ti/Al/Ni/Au Ohmic contact to AlGaN/GaN high electron mobility transistors

A mechanism of the formation of the bulges on the surface of Ti/Al/Ni/Au Ohmic contact in AlGaN/GaN high electron mobility transistors is proposed. According to the analysis of TEM images and corresponding electron dispersive x-ray spectra, the bulges were found to consist of Ni–Al alloy in the body and Au–Al alloy surrounding. We deduce that the bulges were formed due to Ni–Al alloy aggregation in some local areas during the rapid thermal annealing process, which accounts for the rough surface morphology.

Fabrication of Normally Off AlGaN/GaN MOSFET Using a Self-Terminating Gate Recess Etching Technique

A self-terminating gate recess etching technique is first proposed to fabricate normally off AlGaN/GaN MOSFET. The gate recess process includes a thermal oxidation of the AlGaN barrier layer for 40 min at 615°C followed by 45-min etching in potassium hydroxide solution at 70°C, which is found to be self-terminated at the AlGaN/GaN interface with negligible effect on the underlying GaN layer, manifesting itself easy to control, highly repeatable, and promising for industrialization. The fabricated device based on this technique with atomic layer deposition Al2O3 as gate insulator exhibits a threshold voltage as high as 3.2 V with a maximum drain current over 200 mA/mm and a 60% increased breakdown voltage than that of the conventional high electron mobility transistors.

A GaN HEMT Structure Allowing Self-Terminated, Plasma-Free Etching for High-Uniformity, High-Mobility Enhancement-Mode Devices

In this letter, a plasma-free etch stop structure is developed for GaN HEMT toward enhancement-mode operation. The self-terminated precision gate recess is realized by inserting a thin AlN/GaN bilayer in the AlGaN barrier layer. The gate recess is stopped automatically at the GaN insertion layer after high-temperature oxidation and wet etch, leaving a thin AlGaN barrier to maintain a quantum well channel that is normally pinched off. With addition of an Al2O3 gate dielectric, quasi normally OFF GaN MOSHEMTs have been fabricated with high threshold uniformity and low ON-resistance comparable with the normally ON devices on the same wafer. A high channel mobility of 1400 cm2/V·s was obtained due to the preservation of the high electron mobility in the quantum-well channel under the gate.

Oxidation-based wet-etching method for AlGaN/GaN structure with different oxidation times and temperatures

In this article, a detailed analysis of the wet-etching technique for AlGaN/GaN heterostructure using dry thermal oxidation followed by a wet alkali etching was performed. The experimental results show that the oxidation plays a key role in the wet-etching method and the etching depth is mainly determined by the oxidation temperature and time. The correlation of etching roughness with oxidation time and temperature was investigated. It is found that there exists a critical oxidation temperature in the oxidation process. Finally, a physical explanation of the oxidation procedure for AlGaN layer was given.

Demonstration of Normally-Off Recess-Gated AlGaN/GaN MOSFET Using GaN Cap Layer as Recess Mask

Based on our proposed self-terminating gate recess etching technique, normally-off recess-gated AlGaN/GaN MOSFET has been demonstrated with a novel method using GaN cap layer (CL) as recess mask, which, as a result, simplifies the device fabrication process and lowers the fabrication cost. The GaN CL is capable of acting as an effective recess mask for the gate recess process, which includes a thermal oxidation for 45 min at 650 °C followed by 4-min etching in potassium hydroxide (KOH) at 70°C. After gate recess process, no obvious change is observed in terms of the surface morphology of the GaN CL, the contact resistance of the Ohmic contact formed directly on the GaN CL as well as the sheet resistance of the two-dimensional electron gas (2-DEG) channel layer under the GaN CL. The fabricated device exhibits a threshold voltage (Vth) as high as 5 V, a maximum drain current (Idmax) of ~200 mA/mm, a high ON/OFF current ratio of ~1010 together with a low forward gate leakage current of ~10-5 mA/mm. Meanwhile, the OFF-state breakdown voltage (Vbr) of the device with gate-drain distance of 6 μm is 450 V.

Enhancement Mode (E-Mode) AlGaN/GaN MOSFET With

Postgate annealing (PGA) in N2/O2 atmosphere at 300°C for various annealing time is performed on enhancement mode AlGaN/GaN MOSFET fabricated using a self-terminating gate recess etching technique. After 45-min annealing, the device OFF-state leakage current decreases by more than two orders of magnitude and thus a low OFF-state leakage current of 10-13 A/mm is obtained at room temperature, resulting in an excellent ON/OFF current ratio of ~1012. At 250°C, the device still exhibits a low OFF-state leakage current of ~10-9 A/mm and high ON/OFF current ratio of ~108. Meanwhile, a strong correlation between the OFF-state leakage current and mesa isolation current is observed as we change the annealing time: 1) the lower the mesa isolation current and 2) the lower the OFFstate leakage current and thus the higher the ON/OFF current ratio. It is the suppression of the mesa isolation current owing to the passivation of atomic layer deposition Al2O3 that leads to the improvement of the OFF-state leakage current and ON/OFF current ratio after PGA. Besides, the device shows no obvious change in terms of its threshold voltage and maximum drain current after PGA.

10^{-13}

Abstract Ti/Al/Ni/Au (200/1200/500/2000xa0A) Ohmic contact on AlGaN/GaN was prepared and it was subjected to thermal aging experiments. Thermal processing at 400 and 500xa0°C did not change the contact resistance significantly, while high temperature storage at 600xa0°C resulted in a surge in the contact resistance. The Al–Au alloy in the contact metal is believed to re-melt because its lowest melting temperature is 525xa0°C. The liquid of Al–Au alloy is observed to diffuse to the AlGaN surface and consume some AlGaN layer. In addition, voids are found to be produced during thermal process, which can reduce the effective contact area and thus lead to higher contact resistance. The TEM and EDX results of Ohmic contact’s cross sectional images provide evidence for this proposed mechanism.

A/mm Leakage Current and

A novel stacked Ti/Al based Ti/Al/Ti/Al/Ti/Al/Ti/Al/Ni/Au Ohmic contact structure is optimized. Compared with the conventional alloyed Ti/Al/Ni/Au Ohmic contact structure, the novel Ohmic contact structure can obtain much lower contact resistance and specific contact resistivity. Through analysis of x-ray diffraction spectra, cross-section transmission electron microscopy images and corresponding electron dispersive x-ray spectroscopy spectra in the novel stacked Ti/Al based Ohmic structure, the reactions between metals and the AlGaN layer were proven to be stable, uniform and continuous, which produced smooth contact interface. In addition, the top Au layer was prevented from diffusing downwards to the metal/AlGaN interface, which degraded the Ohmic performance.

10^{12}

We report on an AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) using thermal oxidation of electron-beam deposited aluminum as the gate dielectric. This novel dielectric deposition process is simple, and less expensive than electron cyclotron resonance (ECR) plasma oxidation of Al or atomic layer deposited (ALD) Al2O3. The X-ray Photoelectron Spectroscopy (XPS) Ols spectrum showed that the Al2O3 with a bandgap of 7.8 eV was obtained in this specimen. The resulted MOS-HEMT exhibits several orders of magnitude lower gate leakage, larger drain saturation current and larger gate voltage swing compared to a conventional AlGaN/GaN high-electron-mobility transistor (HEMT) of similar design. The MOS-HEMT is therefore a viable alternative to regular HEMTs for high-power, high-frequency and high-temperature applications.

ON/OFF Current Ratio

Abstract In this paper the hot carrier degradation behavior of the SOI dynamic-threshold-voltage nMOSFET’s (n-DTMOSFET’s) is investigated based on the forward gated-diode configuration. With peak diode current as an indicator, the hot carrier induced degradation of SOI n-DTMOSFET’s is compared with the corresponding SOI nMOSFET’s. Due to the connection of the gate and the body and thus the positive-biased source–body and drain–body junction, the SOI n-DTMOSFET’s exhibit lower peak diode current than the conventional counterparts, showing smaller generated defect density and thus lower hot carrier induced degradation. The generated defect distribution in SOI n-DTMOSFET is analyzed. It is shown that despite of the tied gate-body, the peak of the generated defect density tends to lie in the gate-to-drain overlap region. The defect distribution exerts different influences on the diode current of the long channel device and short channel device with different electric field. Moreover, even with the positive biased body, the generated defects in SOI DTMOSFT are more apt to flow to front interface rather than back interface, resulting in the more severe degradation of the front interface in SOI n-DTMOSFET’s. This gives the main flow direction of the generated defects.