Bing-Yue Tsui

High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric

High-performance low-temperature poly-Si thin-film transistors (TFTs) using high-/spl kappa/ (HfO/sub 2/) gate dielectric is demonstrated for the first time. Because of the high gate capacitance density and thin equivalent-oxide thickness contributed by the high-/spl kappa/ gate dielectric, excellent device performance can be achieved including high driving current, low subthreshold swing, low threshold voltage, and high ON/OFF current ratio. It should be noted that the ON-state current of high-/spl kappa/ gate-dielectric TFTs is almost five times higher than that of SiO/sub 2/ gate-dielectric TFTs. Moreover, superior threshold-voltage (V/sub th/) rolloff property is also demonstrated. All of these results suggest that high-/spl kappa/ gate dielectric is a good choice for high-performance TFTs.

Formation of interfacial layer during reactive sputtering of hafnium oxide

Hafnium oxide is one of the most promising high dielectric constant materials to replace silicon dioxide as the gate dielectric. To take the advantages of high dielectric constant of HfO2 thoroughly, the relatively low dielectric constant interfacial layer must be controlled carefully. In this work, the formation of an interfacial SiO2 layer at the HfO2/Si interface was studied comprehensively. It is observed that during reactive sputtering deposition of the HfO2 layer, a very thick interfacial SiO2 layer, thicker than 3 nm, would be grown. O-radical signals, instead of O2-radicl signals, are detected in the sputtering chamber. An O-radical enhanced oxidation model is proposed to explain such an unusual thick SiO2 layer. The adoption of a two-step deposition method, the thickness of interfacial SiO2 layer can be reduced only if the bottom Hf layer is thicker than 5 nm. However, the reduction of effective oxide thickness would be limited. Reoxidation of Hf film sounds a better choice. A 1.0–1.5-nm-thick interfacial SiO2 layer is still observed. This implies that the traced oxygen in the sputtering chamber plays a critical role on the formation of the interfacial layer. It is thus concluded that reactive sputtering is not a suitable method to prepare a HfO2 layer with a negligible interfacial SiO2 layer. Reoxidation of Hf film is a better choice, but the oxygen content in the sputtering chamber must be well controlled.Hafnium oxide is one of the most promising high dielectric constant materials to replace silicon dioxide as the gate dielectric. To take the advantages of high dielectric constant of HfO2 thoroughly, the relatively low dielectric constant interfacial layer must be controlled carefully. In this work, the formation of an interfacial SiO2 layer at the HfO2/Si interface was studied comprehensively. It is observed that during reactive sputtering deposition of the HfO2 layer, a very thick interfacial SiO2 layer, thicker than 3 nm, would be grown. O-radical signals, instead of O2-radicl signals, are detected in the sputtering chamber. An O-radical enhanced oxidation model is proposed to explain such an unusual thick SiO2 layer. The adoption of a two-step deposition method, the thickness of interfacial SiO2 layer can be reduced only if the bottom Hf layer is thicker than 5 nm. However, the reduction of effective oxide thickness would be limited. Reoxidation of Hf film sounds a better choice. A 1.0–1.5-nm-thick in...

Anisotropic thermal conductivity of nanoporous silica film

In this paper, thermal conductivity of porous silica film with porosity from 21 to 64% was studied comprehensively. The corresponded dielectric constant is from 2.5 to 1.5. It is observed that the porous silica material has strong anisotropic characteristic. A serial-parallel hybrid model is proposed to explain the correlation between porosity and thermal conductivity in both in-plane and cross-plane components. The pores in the higher porosity silica film tend to distribute horizontally. This distribution of the pores in the dielectric film is the main factor that induces the anisotropic characteristic. The nonuniform distribution of pores also makes the conventional two-dimensional model of 3u/spl grave/ method inappropriate for extracting the in-plane thermal conductivity. A new method based on the hybrid model was proposed to extract the in-plane thermal conductivity successfully. The anisotropic characteristic of the thermal conductivity may be accompanied by the anisotropic dielectric constant, which will greatly complicate the thermal management and resistance-capacitance delay simulation of the circuits and should be avoided. The proposed model would be helpful on evaluation of new porous low dielectric constant materials.

Process and Characteristics of Fully Silicided Source/Drain (FSD) Thin-Film Transistors

In this paper, high-performance fully silicided source/drain (FSD) thin-film transistors (TFTs) with FSD and ul-trashort source/drain extension (SDE) fabricated by the implant-to-silicide (ITS) technique are studied thoroughly. Using the ITS technique, not only the implantation damage but also the silicide spiking is avoided so that the thermal budget can be decreased obviously. The offstate current (Ioff) of the FSD TFTs is equal to (n-channel) or smaller than (p-channel) that of the conventional TFTs. At onstate, due to the FSD and the SDE structure, the parasitic resistance of the S/D region and the carrier-injection resistance between silicide and channel are reduced. Therefore, superior onstate/offstate current ratio can be obtained. The influences of annealing temperature and time are also examined in this paper. A 600degC/30-s rapid thermal annealing is sufficient to diffuse and activate dopants and, then, fabricate high-performance FSD TFTs. Excellent short-channel behavior of the FSD TFT is also confirmed. To conclude, the high-performance FSD TFT with low parasitic resistance fabricated by low-thermal-budget process is very promising for active-matrix liquid-crystal display, active-matrix organic light-emitting-diode display, and system-on-panel applications

Process and characteristics of modified Schottky barrier (MSB) p-channel FinFETs

A novel modified Schottky barrier p-channel FinFET (MSB FinFET) has been successfully demonstrated previously. In this paper, the detailed process conditions, especially the formation of MSB junctions, has been presented. Device characteristics as well as the geometry effect are also discussed extensively. In the MSB FinFETs fabricated by the two-step silicidation and implant-to-silicide techniques (ITS), an ultrashort and defect-free source/drain extension (SDE) could be formed at a temperature as low as 600/spl deg/C, resulting in excellent electrical characteristics. The ultrashort SDE could effectively thin out the SB width between source/channel during on-state or broaden and elevate it between drain/channel during off-state. A leakage mechanism of MSB FinFETs similar to the conventional ones was identified by the activation energy analysis. Strong fin width dependence of the electrical characteristics was also found in the proposed devices. When the fin width becomes larger than the silicide grain size, the multigrain structure results in a rough front edge of the MSB junction, which in turn degrades the short-channel device performance. This result indicates that the MSB device is suitable for use as FinFET. The low thermal budget of the MSB FinFET relaxes the thermal stability issue for metal gate/high-/spl kappa/ dielectric integration. It is considered that the proposed MSB FinFET is a very promising nanodevice.

Electrical instability of low-dielectric constant diffusion barrier film (a-SiC:H) for copper interconnect

An a-SiC:H deposited by CVD system is the most promising dielectric diffusion barrier to replace silicon nitride in the Cu-interconnect structure due to its low dielectric constant, good Cu barrier ability, and low moisture uptake. In this paper, electrical instabilities of a-SiC:H film under electric field were reported for the first time. At electric field higher than 1.8 MV/cm and independent of the polarity, charges will be built up in the SiC film even at room temperature. A dielectric polarization model was proposed to explain this high field instability. The formation of molecular dipole is attributed to the incorporated nitrogen atoms, which distort the symmetric tetrahedral SiC molecule. The dielectric polarization is further verified by the increase of dielectric constant at high temperature and low frequency. At elevated temperature, film instability can be observed at electric field as low as 0.4 MV/cm. A carrier injection model combined with the polarization was proposed to explain the low-field instability. It is assumed that slight polarization occurs at such a low electric field because of high temperature. The dominant mechanism is electron injection from metal gate into SiC film via the Schottky emission process. It is thus recommended that the incorporation of nitrogen must be minimized and the film stability must be carefully evaluated at real circuit level.

Series resistance of self-aligned silicided source/drain structure

The external resistance of the self-aligned silicided source/drain structure is examined by two-dimensional simulation considering recession of the contact interface due to the consumption of silicon during the silicidation process. It is observed that the recessed contact interface forces a significant amount of current to flow into the high-resistivity part of the junction, resulting in an increase of resistance as large as several hundred ohms-micrometers in comparison with the surface contact structure. The increase scales up with the scaledown of the minimum feature size, and the expected benefits of the salicide structure diminish for the sub-half-micrometer devices. A simple analytical explanation is proposed. By considering the recession of the contact interface, the reported high external resistance of short-channel MOSFETs is explained. Different source/drain contact types are compared, and it is concluded that the conventional salicide process should be modified for sub-half-micrometer devices. >

A comprehensive study on the FIBL of nanoscale MOSFETs

Fringing-induced barrier lowering (FIBL) effect on nanoscale MOSFET is comprehensively examined. It is observed that by combining stack gate dielectric, conductive spacer, short sidewall spacer, and minimum gate/drain (G/D) overlap, the I/sub off/ with a dielectric constant of (k) 100 is only 1.6 times higher than that with k=3.9 when the gate length is 25 nm. The fully depleted silicon-on-insulator device shows even better FIBL immunity. It is concluded that although the FIBL effect can not be eliminated, it would not an issue beyond the 45-nm technology node.

Investigation of molybdenum nitride gate on SiO2 and HfO2 for MOSFET application

It has been reported that the work function of nitrided molybdenum (MoN) can be modulated by the atomic ratio of N/Mo and is suitable for gate material of complementary metal oxide semiconductor devices. In this work, we investigated the characteristics of MoN x prepared by reactively sputtering deposition from the gate electrode point of view. The main phase of the MoN x films is MoN(200). As the N/Mo ratio increases, the microstructure of MoN x film tends to be amorphous-like and the resistivity increases. After high-temperature annealing, the phase remains stable and grain size increases slightly. The HfO 2 film has better immunity to sputtering damage than SiO 2 film; therefore, the sputtering deposition method could be a choice of metal gate deposition as HfO 2 -based dielectric is used. The work function of MoN x increases with the increase of nitrogen content and tends to saturate at the valence band of Si. No Fermi-pinning effect is observed on HfO 2 film. The work function and thermal stability of MoN x show good thermal stability on both SiO 2 and HfO 2 films up to 800°C at least. All of these results indicate that MoN is a good candidate of gate electrode for p-type metal oxide semiconductor field effect transistors (pMOSFETs) or fully depleted SOI devices.

Spatial and energetic distribution of border traps in the dual-layer HfO2∕SiO2 high-k gate stack by low-frequency capacitance-voltage measurement

Threshold voltage instability measured by the pulse current-voltage technique has been recognized as the transient charging and discharging of the preexisting bulk traps in Hf-based high-k gate dielectrics, and these high-k traps or called border traps can instantly exchange charge carriers with the underlying Si substrate by tunneling through the thin interfacial oxide. Based on an elastic tunneling model through trapezoidal potential barriers, the spatial and energetic distribution of border traps in the HfO2∕SiO2 high-k gate stack can be profiled as a smoothed, three-dimensional mesh by measuring the low-frequency capacitance-voltage characteristics of high-k metal-oxide-semiconductor capacitors with n-type Si substrate.