Pei-Jer Tzeng

Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration

The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed to address the bandwidth challenges between the ASIC and its external memory. This paper presents a novel 3D IC architecture that includes a silicon interposer with Through-Silicon-Vias (TSV) and interconnect wiring layers on both sides of the silicon interposer. An ASIC chip measured at 22 mm × 18 mm × 0.4 mm is attached on top of the silicon interposer while two smaller memory chips with a size of 10 mm × 10 mm × 0.4 mm are attached to the bottom of the silicon interposer with micro-bump interconnections. A unique, double-sided Chip to Chip (C2C) joining process is developed to enable the ASIC and memory integration in true 3D System-in-Package (SiP) format. This 3D IC architecture will help to overcome the size limitation of the current silicon interposers due to the reticle size used in the lithographic wafer processing. The 3D IC stack is assembled on an organic package substrate with conventional solder bumps. Communications between the top ASIC die and the bottom memory dice are made through the TSVs and the wiring layers of the silicon interposer. Thermal and thermo-mechanical analysis of the 3D IC stack are used to evaluate the package thermal performance and for optimizing material selection and package reliability. Both the modeling and experimental characterization results are used to gain insights into the 3D IC technology for addressing the ASIC and memory bandwidth challenges and to develop the best practice for ASIC and memory integration for next generation high performance network systems.

Fine-pitch backside via-last TSV process with optimization on temporary glue and bonding conditions

Fine-pitch backside via last through silicon via (TSV) process flow is demonstrated as a qualified candidate to be used in the construction of 3D-IC structure. Glue and its bonding conditions are critical to the final yield of the process. Different glues and temporary bonding conditions are investigated to find out the optimized stable process flow. Different daisy chain lengths are used to evaluate the maturity of the backside via last TSV process.

Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers

The effects of etch rate on TSV sidewall variation in 8” (200mm) and 12” (300mm) wafers are investigated in this study. Emphasis is placed on the determination of sidewall scallop with different etch rates ranging from 1.7μm/min to 18μm/min and various TSV diameters (1μm, 10μm, 20μm, 30μm, and 50μm) by design of experiments (DoE). The BHE in/out (2666Pa/2666Pa) are the same for all the cases. Also, characterizations of the sidewall scallop are performed by cross sections and scanning electron microscopy (SEM). Furthermore, with a same etch recipe, mask, and 9 (5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 40μm, 55μm, and 65μm) TSV diameters, the etch results such as etch rate, TSV depth, and sidewall scallop of 200 and 300mm wafers are provided and compared, Finally, a set of useful process guidelines and recipes for optimal TSV etching is presented.

Impact of slurry in Cu CMP (chemical mechanical polishing) on Cu topography of Through Silicon Vias (TSVs), re-distribution layers, and Cu exposure

In this study, the optimization of Cu CMP performance (dishing) for removing thick Cu plating overburden due to Cu plating for deep TSVs in a 300mm wafer is investigated. Also, backside isolation oxide CMP for TSV Cu exposure is discussed. In order to obtain a minimum Cu dishing on the TSV region, a proper selection of Cu slurries is proposed for the current two-step Cu polishing process. The bulk of Cu is removed with the slurry of high Cu removal rate at the first step and the Cu surface is planarized with the slurry of high Cu passivation capability at the second step. The Cu dishing can be improved up to 97% for the 10μm-diameter TSVs on a 300mm wafer. The dishing/erosion of the metal/oxide can be reduced with respect to a correspondingly-optimized Cu plating overburden for TSVs and RDLs. Cu metal dishing can be drastically reduced once the Cu overburdens are increased to a critical thickness. For backside isolation oxide CMP for TSV Cu exposure, the results show that the Cu studs of TSVs with a bigger via size still keep in a plateau-like shape after CMP.

Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP

In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.

Electrical testing of blind Through-Silicon Via (TSV) for 3D IC integration

In this study, a method to test blind TSVs in 3D IC integration for their electrical performance is investigated. Emphasis is placed on the development of a novel blind-TSV method by electrical testing on the top side of the TSV-wafer before backgrinding. Through leakage current testing, it is possible to determine whether there is short circuit between blind TSVs. Most conventional measurement methods can only be performed after wafer thinning to reveal the TSVs Cu and/or backside processing, which could lead to a higher manufacturing cost of 3D IC integration products if the electrical performances of the manufactured TSV dont meet the specification. Also, by providing analysis flow of high frequency simulation and measurement, we can define the thickness of the isolation layer (Silicon dioxide, SiO2) of blind TSV into specification. Furthermore, the analysis flow can obtain the important high-frequency parameter of silicon material such as silicon conductivity. Finally, the SEM images of cross sections verify the current findings.

A thermal performance measurement method for blind through silicon vias (TSVs) in a 300mm wafer

This paper demonstrates an effective TSV test-key and the coupled measurement method to determine TSVs (through-silicon vias) thermal integrity before wafer thinning by using a thermal measuring technique. The test-key comprises two linear metallic traces with the same shape which are deposited on a silicon wafer: one coupled with a line of embedded blind vias, the other coupled without any via. By measuring the thermal resistance difference (ΔR) between both traces and comparing it with a calculated “low bar” of ΔR, one can easily diagnose the TSVs and determine there are seams/voids or not. To verify the method, the TSV test-keys in a 300mm silicon wafer with 750μm thick are fabricated. The measured results show the test-key can produce a ΔR that is large enough to measure and are in good agreement with the simulation results. In this study, we also provide some techniques to shorten the measurement time as well as the guidelines to help users designing their test-key.

Design, fabrication, and calibration of stress sensors embedded in a TSV interposer in a 300mm wafer

In this study, the design, fabrication, and calibration of the piezoresistive stress sensors [1-18] embedded in a TSV (through silicon via) interposer in a 300mm wafer are investigated. The results presented herein should be useful for the development of 3D integration such as measuring the strength of the TSV device and interposer wafers, during and after all the processes such as wafer thinning, SiO2 deposition, metallization, and electroplating.

Process integration for backside illuminated image sensor stacked with Analog-to-Digital Conversion chip

In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of a 3 Mega pixel CMOS image sensor is temporary bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside. The backside is then permanently bonded to a glass carrier substrate with a transparent thermal set bonding material. After the glass permanent bonding process, the temporary bonded silicon carrier could be removed. Cu/Sn micro-bump is fabricated at the front-side of the CMOS image sensor, thus no TSVs are needed in the proposed structure. A 3 Mega pixel CMOS wafer with micro-bumps bonded on 500 μm-thick glass wafer is demonstrated. Void-free bonding is obtained both in temporary bonding and permanent bonding processes. The thickness of the CMOS image sensor wafer is less than 10 μm after thinning and the total thickness variation is around 1 μm. Thermal plastic material is used for temporary bonding because it flows during bonding process and resulted in excellent planarization. From the cross-section SEM image, Cu/Sn micro-bump is formed at the front-side of the CMOS image sensor and the ENIG UBM is formed on the front side of the Analog-to-Digital Conversion wafer. A 3 Mega pixel image is captured and demonstrated in this research. The proposed backside illuminated CMOS image sensor structure and process integration are processed in wafer level, therefore enabling a low cost technology which can be manufactured using existing infrastructure. By using thin wafer handling technology, direct fusion bond and TSV processes are not needed which provides a low cost wafer level solution.

Fully 3-D symmetrical TSV monolithic transformer for RFIC

Two integrated passive device (IPD) structures are proposed in this paper. The first structure is a differential symmetrical through-silicon via (TSV) monolithic transformer that exhibited optimal symmetry between the two ends of the primary and secondary coils, enabling the operation of a differential circuit. The second structure is a fully 3-D symmetrical TSV monolithic transformer that differs from 3-D TSV transformers proposed in the literature. In addition to the optimal symmetry between the two ends of the primary and secondary coils, the primary and secondary coils also exhibited optimal symmetry. In this study, test keys with 1:2 and 1:3 transformer turns ratios were applied to the structure of a differential symmetrical transformer. The fully 3-D symmetrical TSV monolithic structure was designed as a test key with a true 1:1 turns ratio. The TSV of all test keys exhibited a 5 μm diameter, 60 μm depth, and 20 μm pitch. These test keys were simulated using HFSS, a fully 3-D simulator, and fabricated on a 300 mm wafer by using the ITRIs 3-D integrated circuit back-end-of-line process. The simulation results indicated that the inductance of the primary and second coils was 514 and 520 pH, respectively. The coils exhibited a Q factor of 12.08 and 11.98, respectively, when operated at 15 GHz, and the relative difference between the two coils was 1.15%. Compared with transformer structures proposed in the literature, the structure proposed in the present study exhibited superior symmetry between the primary and secondary coils.