Binghai Liu

Top-down delayering to expose large inspection area on die side-edge with Platinum (Pt) deposition technique

Abstract The shrinking in feature sizes of semiconductor devices from integrated circuit (IC) 1 and function complexity has led to greater PFA 2 delayering challenges. The challenges stem from incorporation of top thick hard Silicon Dioxide (SiO 2 ) material that is formed from Tetra Ethyl Ortho Silicate (TEOS) 3 as Inter-Metal Dielectric (IMD) 4 and very thin ultra low-k dielectric material. For a device in copper (Cu) metal line technology, it is almost impossible to expose the entire layer at the same surface flatness by using a conventional top down polishing method, especially at the interface on TEOS and ultra low-k layer where dies side-edge is always thinner than die center (edging effect). Hence, for cases that required PFA delayering on the die side-edge especially for those packaged device or skeleton die, it is extremely challenging for PFA skillset. This paper outlines a proposed technique; perform Platinum (Pt) deposition on the selective area to slow down the side-edging effect. This proposed technique is easy and less skillset dependent to deprocess sample for defect identification analysis.

Failure analysis on 14 nm FinFET devices with ESD CDM failure

Abstract Electrostatic Discharge (ESD) is an important area for the semiconductor industry because ESD has an impact on production yield and product quality. ESD problems are increasing and have become challenging in the semiconductor industry because of the trends toward higher speed and shrinking in technology node. By continually shrinking the transistor with technology scaling, the process, circuit design, and failure analysis (FA) are getting more challenging. This paper is about FA on a 14 nm Fin-Field Effect Transistor (FinFET) device which has ESD failure after Charged Device Model (CDM) test. In most ESD failure FA, most of the time found Electrical Over Stress (EOS), the important is to understand which process layer or design causing the EOS. At the same time, this paper also discusses the difficulties faced, the FA technique used, the bottleneck of the 14 nm FinFET FA by old technology node FA equipment, and the FA findings. Finally, the ESD failure was identified with Scanning Transmission Electron Microscope (STEM)/Energy Dispersive Spectroscopy (EDS) analysis. The FA findings of the failure are related to the front end of line (FEOL), the metal gate of FinFET was fused with active, and the material in the metal gate was out-diffused.

Cross-sectional nanoprobing sample preparation on sub-micron device with fast laser grooving technique

Abstract Cross-sectional sample preparation is one of the most important failure analysis (FA) techniques in the semiconductor industry. It was commonly used for film stack critical dimension measurement, defect identification, electrical fault isolation and etc. However, cross-sectional sample preparation to a specific target location on a sub-micron device is very challenging and time-consuming. This is because of mechanical polishing easily caused metal smear, delamination, film peel-off, micro-cracked and etc. This paper focused on cross-sectional nanoprobing (XNP) sample preparation improvement in quality and quantity. A laser blast to deprocess or create a groove at near to target location before conventional mechanical polishing and focus ion beam (FIB) fine milling. The proposed technique not only reduces the sample preparation time to the sub-micron target location but also prevent mechanical damages that caused by mechanical polishing technique.

A developed wedge fixtures assisted high precision TEM samples pre-thinning method: Towards the batch lamella preparation

Ion milling, wedge cutting or polishing, and focused ion beam (FIB) milling are widely-used techniques for the transmission electron microscope (TEM) sample preparation. Especially, the FIB milling provides a site-specific analysis, deposition, and ablation of materials in the micrometer and nanometer scale. However, the cost of FIB tools has been always a significant concern. Since it is inevitable to use the FIB technique, the improvement of efficiency is a key point. Traditional TEM sample preparation with FIB was routinely implemented on a single sample each time. Aiming at cost efficiency, a new pre-thinning technique for batch sample preparation was developed in this paper. The present proposal combines the sample preparation techniques with multi-samples thinning, cross-section scanning electron microscopy (SEM), wedge cutting, FIB and other sample pre-thinning techniques. The new pre-thinning technique is to prepare an edge TEM sample on a grinding and polishing fixture with a slant surface. The t...

Study on fab environment induced Al and Cu metal corrosion by TEM failure analysis

Contamination-free manufacturing environment is essential for semiconductor wafer fabs. Any contaminants from production line such as process tools and chambers need to be closely monitored and well controlled so as to avoid the direct exposure of the production wafers to these contaminants. In this paper, we discussed two typical metal corrosion issues induced by wafer fab environmental contamination, i.e. aluminum (Al) metal corrosion by fluorine (F)/chlorine (Cl), copper (Cu) metal corrosion by iodine (I). We presented detailed transmission electron microscope (TEM) analysis of the defects related to metal corrosion, helping fabs to identify the root cause and to take corrective actions.

Application of laser deprocessing technique in PFA on chemical over-etched on bond-pad issue

Abstract With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) 1 design and function complexity, the package size has shrank down proportionally too. Hence, flip-chip solder bump mounting is the current semiconductor devices trend to replace the wire bonding technology. When come to PFA 2 on the flip-chip devices with solder bump, wet etch for solder bump removal is an essential method. Upon using wet etch methodology; it is very dependent on etching timing and the chemical aggressiveness to get a good removal result for the solder bump. If there is an excessive period in etching or chemical reacts too aggressively, chemical over-etched on bond pad will occur. It is very unfavorable for FA 3 engineer to perform subsequent reverse engineering on the bond pad over-etched device. In this paper, the application of laser deprocessing technique is proposed to solve the bond pad over-etched issue. This proposed technique is a quick and reversal way in deprocessing technique for defect identification in PFA.

Application of Fast Laser Deprocessing Techniques on large cross-sectional view area sample with FIB-SEM dual beam system

Abstract Cross-sectional analysis is one of the important areas for physical failure analysis. Focus Ion Beam (FIB) and mechanical polish sample preparation are commonly used and necessary techniques in the semiconductor industry and Failure Analysis (FA) Company (Wills and Perungulam, 2007). However, each technique has its own limitation. Mechanical polishing technique easily induces artifact by mechanical force, especially on advance technology node. FIB can eliminate mechanically damaged artifact, but have the limitation on cross-sectional view area. Another potential technique will be plasma FIB, it used very high milling current and fast milling speed (Hrnciř et al., 2013). However, it comes with a very high cost and having the contamination issue. The contamination issue greatly affects the low kV Scanning Electron Microscopy (SEM) imaging quality. In recent semiconductor industry FA, low kV SEM imaging is preferable, because high kV imaging will introduce delamination artifacts especially on organic material from packaged sample. In this paper, Fast Laser Deprocessing Techniques (FLDT) application is further enhanced on large area cross-sectional FA with fast cycle time and low-cost equipment. This is to prevent from mechanical damage. In short, the proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in cross-sectional FA.

A sample preparation methodology to reduce sample edge unevenness and improve efficiency in delayering the 20-nm node IC chips

With continuous scaling of Complementary Metal Oxide Semicondutor (CMOS) device dimensions, traditional inter-level dielectrics have be replaced by low-k materials, because of the advantages of ultra low-k material such as lower parasitic capacitance, lower cross talk effects, and lower RC delay. The new material in integrated circuits (IC) makes physical failure analysis (PFA) more challenging. This paper presents a sample preparation methodology for reducing the sample deprocess edging effect with an efficient way on delayering the 20-nm node IC chips. We combined several delayering techniques to achieve an excellent flatness surface and improve the time efficiency for PFA on 20nm technology.

A new localized ink coating methodology for preventing photoresist deformation for TEM sample preparation

In this work we reported a new methodology for ink coating for TEM sample preparation. Detailed pre-FIB and FIB processes were performed under different conditions such as method of coating used and baking temperatures. TEM profile was taken on all prepared sample to understand the critical dimensions of PR under various conditions, and a comparison was made to conclude the best coating method to minimize PR profile deformation during sample preparation. Finally, a new technique of using static glass needle to apply ink coating was introduced to enhance coating application on very localized site specific structures.

Study on the poly bump defect by TEM failure analysis

In this work we reported TEM failure analysis of an inline defect issue, nanosized poly bump defect formed during poly CVD process. Detailed TEM analysis was performed for the characterization of microstructure and composition of the nanosized defects by using various TEM FA techniques, including EDX, EELS analysis. It was found out that underneath the poly bump defect had a core-shell structure, i.e. oxide core with poly-Si shell. We demonstrated the importance of TEM sample preparation and the selection of suitable TEM FA techniques for the characterization of such nanosized defects for root-cause understanding.