Adam Brand

Semiconductor Logic Technology Innovation to Achieve Sub-10 nm Manufacturing

Moores Law represents the cumulative effort by many participants to advance the productivity of electronic systems over the last 40+ years, resulting in enormous strides in the capability and ubiquity of electronics. This paper identifies the innovation challenges the semiconductor industry must overcome in order to propel the advance of semiconductor technology to the cadence of Moores Law. Key examples will highlight the solutions needed to enable advanced transistor and nano-scale interconnect fabrication. Solutions for tomorrows low voltage, low power process technologies will introduce new materials, unprecedented levels of interface control and new energy sources while at the same time addressing the increasing cost and complexity needed to sustain Moores Law well into the future.

15nm-W FIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET_INV-normalized G_M,SAT,INT of 6.7 nm.mS/μm, the Si_0.3Ge_0.7 / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.

Is strain engineering scalable in FinFET era?: Teaching the old dog some new tricks

S/D epitaxy remains an effective source of strain engineering for both aggressively and conservatively scaled FinFETs. Not merging the S/D epitaxy between adjacent fins and recess etch into the fin before S/D epitaxy is recommended for maximizing the gain. With high active P concentration Si:C becomes an effective stressor for NMOS. Contact and gate metal fills provide new knobs for engineering strain in FinFET devices for the 22nm node and remain effective with conservative scaling of contact / gate CD only.

Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET

We report a record setting low NMOS contact Rc of 2e-9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e-9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity with HD Si:P using P implantation followed by laser anneal to reach the contact resistivity requirement for the 10nm or 7 nm nodes.

Highly scalable bulk FinFET Devices with Multi-V T options by conductive metal gate stack tuning for the 10-nm node and beyond

A scalable multi-VT enabled RMG CMOS integration process with highly conformal ALD TiN/TiAl/TiN is described. The multi-VT is implemented by metal gate tuning using two different options. The first relies on bottom-barrier thickness control, the second on implantation of nitrogen into the work function metal. A shift in the effective work function (eWF) of ~400 mV is realized by adjusting the TiN bottom barrier thickness underneath TiAl, while over 200 mV shifts are achieved by means of implantation of nitrogen into ALD TiN/TiAl/TiN. The gate-stack Tinv, JG, DIT and reliability as well as the device performance are shown to be unaffected by the multi VT process.

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (VT) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (JG). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-VT: 1) conformal, lower-JG ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.

Gate-first TiAlN P-gate electrode for cost effective high-k metal gate implementation

Gate-first (GF) high-k metal gate (HKMG) for LSTP/LOP logic and DRAM periphery applications requires an efficient and low-cost effective work function (eWF) solution. We demonstrated TiAlN for pFET eWF tuning without appreciable EOT, Jg, and interface degradation. Hence TiAlN is shown to be a key enabler to realize process-friendly and cost-effective GF HKMG implementation.

Metal gate work function modulation by ion implantation for multiple threshold voltage FinFET devices

FinFET has emerged as a device structure to enable the device scaling at and beyond the 22nm technology node due to increasingly stringent demands for maximum device speed, lower leakage current and control of random dopant fluctuation effects. High-k dielectric (Hik)/metal gate (MG) technology makes it feasible to obtain improved Effective Oxide Thickness (EOT) scaling and reduced leakage. Replacement metal gate (RMG) flows have been used for high performance logic volume production at and beyond 45nm node [1]. Precise threshold voltage (Vt) control and multiple Vt are required for FinFET device architectures for future devices. This paper proposes an ion implantation approach for modulating metal gate work function for both n-metal and p-metal gate used in a HiK last and replacement gate process. This approach offers simplified integration flow where no additional mask is needed and resist mask can be used. The effective work function (eWF) was measured along with the EOT and Gate Leakage (Jg). Stress Induced Leakage Current (SILC) method was used for testing HiK stack reliability. The results showed up to 200mV eWF modulation by ion implantation with fine control and without EOT and Jg degradation. The effect of implant species and dose on the eWF was studied in this paper. SIMS analysis of HKMG stack on the blanket wafer was used to determine the dopant distribution and explore the possible mechanism for metal gate work function modulation by ion implantation.

RMG nMOS 1 st process enabling 10x lower gate resistivity in N7 bulk FinFETs

A novel RMG process in which the n-type work function metal (nWFM) is deposited first and then selectively removed from the pMOS devices is presented for the first time. The key benefit of this nMOS 1st process lies in increased gate-fill space which results in about 10× improvement in the pMOS effective gate resistivity at gate lengths (LG) around 22 nm, an improvement which is predicted by modeling to extend down to LG<;14 nm. The complete removal of the nWFM in the pMOS devices is evidenced by restored p-type effective work function (eWF) values in large area capacitors and matched pMOS threshold voltage (VT) values in bulk FinFET devices with LG down to 22 nm. Furthermore, selective removal of the nWFM is confirmed physically down to LG~16 nm providing further evidence that the process is scalable towards N7 dimensions.

Replacement metal gate extendible to 11 nm technology

This paper describes novel Co-Al metal fill capable of filling sub-10nm trenches. Co-Al fill shows advantages in threshold voltage (VTH) variation. The conductivity of the fill was evaluated using a Co-Al alloy conductance model. By demonstrating better VTH variability, superior conductivity and gap fill, Co-Al shows extendibility to the 11nm metal gate and beyond.