Bjorn Zetterlund

A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications

We present the electrical characteristics of the first 90nm SiGe BiCMOS technology developed for production in IBMs large volume 200mm fabrication line. The technology features 300 GHz fT and 360 GHz fMAX high performance SiGe HBTs, 135 GHz fT and 2.5V BVCEO medium breakdown SiGe HBTs, 90nm Low Power RF CMOS, and a full suite of passive devices. A design kit supports custom and analog designs and a library of digital functions aids logic and memory design. The technology supports mm-wave and high-performance RF/Analog applications.

Total Dose and Transient Response of SiGe HBTs from a New 4th-Generation, 90 nm SiGe BiCMOS Technology

The total ionizing dose and laser-induced transient response of a new 4th generation 90 nm IBM SiGe 9HP technology are investigated. Total dose testing was performed with 63.3 MeV protons at the Crocker Nuclear Laboratory at the University of California, Davis. Transient testing was performed on the two-photon absorption system at Naval Research Laboratory. Results show that the SiGe HBTs are dose-tolerant up to 3 Mrad(SiO2) and exhibit reduced single event transients compared to earlier SiGe generations.

Study of mutual and self-thermal resistance in 90nm SiGe HBTs

Impact of mutual thermal coupling on the performance of a single 90nm SiGe heterojunction bipolar transistor (HBT) due to the presence of power dissipating elements like other HBTs in near vicinity is presented in this paper. Mutual thermal resistance (Rth,mutual) has been computed as a function of spacing between the single HBT and a ring of HBTs surrounding the device. HBT structural design variations including device layout schemes, metal wire stack connected to the emitter, deep trench (DT) depth and emitter to DT spacing, for reduced self thermal resistance (Rth), have been explored in this paper. An updated thermal resistance model accounting for the heat flow through the metal wiring stack connected to the emitter is also reported.

A novel Ccb and Rb reduction technique for high-speed SiGe HBTs

In this paper, we discuss a novel technique to reduce base resistance (R_b) and collector-base capacitance (C_cb) for higher F_max in high-speed SiGe HBTs. In order to reduce C_cb, we first located the origins of the different components of C_cb through AC extraction. Then we utilized scanning capacitance measurements (SCM) to examine the shape of the collector-base depletion. We then propose a method to reduce the extrinsic C_cb, namely by using reticle enhancement techniques to print a blocking oxide layer to inhibit boron outdiffusion. An additional benefit was the reduction of R_b by reducing the base link resistance.

Investigation of HBT layout impact on f T doubler performance for 90nm SiGe HBTs

Peak fT of 660 GHz is reported for HBT fT doubler designs in IBM 90 nm SiGe BiCMOS technology 9HP. This high performance fT doubler utilizes a longer HBT for output stage compared to the input stage HBT (length ratio 2:1) resulting in improved transconductance and lower thermal resistance. The impact of HBT layout on the circuit performance and trade-off between thermal resistance and fT is also investigated. fT doubler circuit can be used as a single transistor in several circuit applications like A/D converters and broadband circuits where higher performance is desired.

SiGe HBTs in 90nm BiCMOS technology demonstrating 300GHz/420GHz f T /f MAX through reduced R b and C cb parasitics

Scaling both the fT and the fMAX of SiGe HBTs is quite challenging due to the opposing physical device requirements for improving these figures of merit. In this paper, millisecond anneal techniques, low temperature silicide and low temperature contact processes are shown to be effective in reducing the base resistance. These processes when combined with a novel approach to address the collector-base capacitance are shown to produce high performance SiGe HBT devices which demonstrate operating frequencies of 300/420GHz fT/fMAX. This is the first report of 90nm SiGe BICMOS with an fMAX exceeding 400GHz.

Modeling of U-shaped and plugged emitter resistance of high speed SiGe HBTs

In this paper, we investigate the emitter resistance R<inf>e</inf> in SiGe HBTs with speeds up to 280GHz, using a U-shaped polysilicon emitter. We observed that R<inf>e</inf> increased with lateral scaling, thereby degrading f<inf>T</inf>. Although a negligible component in the past, in this experiment R<inf>e</inf> * C<inf>cb</inf> transit time delay is playing a more significant role in limiting f<inf>T</inf>. R<inf>e</inf> was modeled to explain the increase due to lateral scaling, and was shown to result from the plugging of the emitter opening by the emitter polysilicon. Furthermore, process experiments were conducted to investigate the effect of emitter polysilicon thickness, sidewall height, and emitter i-layer thickness.