Edinei Santin

A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, slew rate, and input/output range are carried out. Based on these analyses, a manual design methodology and a genetic algorithm based optimization are presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13 μm 1.2 V standard CMOS technology are shown.

Two-stage fully-differential inverter-based self-biased CMOS amplifier with high efficiency

This paper describes a novel two-stage fully-differential CMOS amplifier comprising two self-biased inverter stages, with optimum compensation and high efficiency. Although it relies on a class A topology, it is shown through simulations, that it achieves the highest efficiency of its class and comparable to the best class AB amplifiers. Due to the self-biasing, a low variability in the DC gain over process, temperature, and supply is achieved. A detailed circuit analysis, a design methodology for optimization and the most relevant simulation results are presented, together with a final comparison among state-of-the-art amplifiers.

An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification

This brief presents an 8-bit 120-MS/s time-interleaved pipeline analog-to-digital converter (ADC) fully based on MOS discrete-time parametric amplification. The ADC, fabricated in a 130-nm CMOS logic process, features an active area below 0.12 mm2, where only MOS devices are used. Measurement results for a 20-MHz input signal shows that the ADC achieves 39.7 dB of signal-to-noise ratio, 49.3 dB of spurious-free dynamic range, -47.5 dB of total harmonic distortion, 39.1 dB of signal-to-noise-plus-distortion ratio, and 6.2 bits of peak effective number of bits while consuming less than 14 mW from a 1.2-V supply.

A Fully Integrated and Reconfigurable Architecture for Coherent Self-Testing of High Speed Analog-to-Digital Converters

This paper presents a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed analog-to-digital converters (ADCs) with moderate resolutions. The proposed system is suited to be fully integrated with the ADC and, besides a low jitter clock reference, no other external high quality generators are required. The complete system comprises two synchronized phase-locked loops (PLLs), one based on a two-integrator oscillator capable of providing low distortion outputs and another based on a relaxation oscillator providing low jitter squared output, to allow coherent sampling. A detailed description of the building blocks of both PLLs is given as well as the techniques used to minimize area of the loop filters (LFs), to stabilize the output amplitude of the two-integrator oscillator to a known value, and to improve the total harmonic distortion (THD) of this oscillator. Post-layout simulations, in a 0.13 μm CMOS technology, of the proposed BIST scheme applied to a case-study 6-bit 1 GS/s ADC are shown and validate the proposed test methodology.

Fully integrated and reconfigurable architecture for coherent self-testing of IQ ADCs

In this paper we present a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed IQ ADCs with moderate resolutions. The proposed system can be fully integrated with the ADC and, besides a low-jitter clock reference, no other external high quality generators are required. A locked system comprising a first phase-locked loop (PLL) with two IQ linear outputs and a second PLL with a squared output signal are proposed as well as the dedicated voltage-controlled oscillator (VCO) circuits. To illustrate the simplicity of the proposed solution, the system is designed, parameterized and simulated targeting the BIST of a 6-bit 1 GS/s ADC.

A CMOS Inverter-Based Self-biased Fully Differential Amplifier

A CMOS self-biased fully differential amplifier is presented. Due to the self-biasing structure of the amplifier and its associated negative feedback, the amplifier is compensated to achieve low sensitivity to process, supply voltage and temperature (PVT) variations. The output common-mode voltage of the amplifier is adjusted through the same biasing voltages provided by the common-mode feedback (CMFB) circuit. The amplifier core is based on a simple structure that uses two CMOS inverters to amplify the input differential signal. Despite its simple structure, the proposed amplifier is attractive to a wide range of applications, specially those requiring low power and small silicon area. As two examples, a sample-and-hold circuit and a second order multi-bit sigma-delta modulator either employing the proposed amplifier are presented. Besides these application examples, a set of amplifier performance parameters is given.

CMOS Fully Differential Feedforward-Regulated Folded Cascode Amplifier

A fully differential self-biased inverter-based folded cascode amplifier which uses the feedforward-regulated cascode principle is presented. A detailed small-signal analysis covering both the differential-mode and the common-mode paths of the amplifier is provided. Based on these theoretical results a design is given and transistor level simulations validate the theoretical study and also demonstrate the efficiency and usefulness of the proposed amplifier.

Purely-digital versus mixed-signal self-calibration techniques in high-resolution pipeline ADCs

This paper describes and compares some of the most energy and area efficient self-calibration techniques reported over the past years. Additional techniques used to further improve power dissipation are briefly described as well. A robust mixed-signal self-calibration technique is proposed, in which, the multi-bit first stage in the ADC is calibrated without requiring any modifications, as long as the ideal conversion characteristic of this stage is known. A novel Gaussian Noise Generator is used as the input analog stimulus and, on the digital side, the calibration algorithm does not require explicit multiplications, which greatly simplifies the digital circuitry. Experimental measurements of a 13-bit ADC fabricated in 90 nm CMOS, after calibration and at 40 MS/s, show that the SFDR is improved by over 14 dB (to 84 dB), the THD is improved by over 10 dB (to −80 dB), achieving a peak ENOB of 11.3 bits for a 10 MHz input and with a 1.2 V power supply.

Fast and accurate estimation of gain and sample-time mismatches in time-interleaved ADCs using on-chip oscillators

The estimation of inter-channel mismatches in time-interleaved analog-to-digital converters (TI-ADCs) is a crucial step towards the compensation of output errors inherent of these converters. In this paper, we investigate a fast, accurate and low-complexity method for estimation of static gain and sample-time mismatches. The proposed technique uses a calibration signal generated on-chip through a sinusoidal oscillator inserted into a phase-locked loop (PLL), similarly as the sampling clock signal is usually generated in these high speed conversion systems. We synchronize these two PLLs to allow efficient frequency domain computations, without resorting to windowing, from which accurate estimations are feasible. We show that the accuracy of the method is not affected by nonidealities in the calibration signal as long as the calibration frequency is carefully selected.

Fast-settling low-power two-stage self-biased CMOS amplifier using feedforward-regulated cascode devices

A fast-settling two-stage completely self-biased amplifier (op amp) is presented. The op amp uses two amplifying stages and feedforward-regulated cascode transistors to achieve high dc gain, while maintaining a reasonable output swing and high-frequency performance. Exhaustive simulation results over corners demonstrate that, after proper time-domain optimization of the proposed op amp in a 0.13-µm CMOS technology, a very fast settling with accuracy over 12 bits can be achieved, while dissipating very low power.