Ki-Hyun Hwang

Characterization of sputter-deposited LiMn[sub 2]O[sub 4] thin films for rechargeable microbatteries

Thin films of LiMn[sub 2]O[sub 4] spinel were fabricated by RF magnetron sputtering. The as-deposited films were amorphous but could be crystallized into a spinel structure by rapid thermal annealing in an oxygen atmosphere. The electrochemical performance of 2000 [angstrom] thick LiMn[sub 2]O[sub 4] thin-film cathodes were tested in a LiMn[sub 2]O[sub 4]/1M LiClO[sub 4] in PC + DME/Li cell. LiMn[sub 2]O[sub 4] spinel films prepared at 750 C showed good intercalation kinetics and very promising cycling behavior. Room temperature cycling of these films had capacities of about 50 [mu]Ah/cm[sup 2]-[mu]m at 200 [mu]A/cm[sup 2] and maintained more than 98% of their original capacity after more than 1000 cycles.

Mechanism of Surface Roughness in Hydrogen Plasma‐Cleaned (100) Silicon at Low Temperatures

Surface roughening and defect formation of (100) Si at low temperatures during electron cyclotron resonance hydrogen plasma cleaning are studied in an ultrahigh vacuum environment, and a new model is proposed to explain their mechanisms. The effect of process parameters on surface roughness is quantitatively analyzed by atomic force microscopy and reflection high energy electron diffraction. Crystalline defect morphology is studied by transmission electron microscopy to understand its role in surface roughness. Surface roughness is strongly related to {111} platelet defects at the Si subsurface region and subsequent preferential etching at positions where {111} platelet defects intersect the Si surface. The formation of {111} platelet defects is determined by the subsurface hydrogen concentration, which is determined by incident hydrogen flux and substrate temperature. The preferential nucleation of etching reactions on the {111} platelet may be explained by the classical nucleation theory. Hydrogen ion flux and substrate temperature can be controlled successfully to tailor {111} platelet defect formation and hence, surface roughness.

Low-temperature in situ cleaning of silicon (100) surface by electron cyclotron resonance hydrogen plasma

Low‐temperature, defect‐free, in situ cleaning of silicon prior to homoepitaxy is successfully developed by an electron cyclotron resonance hydrogen plasma treatment in an ultrahigh vacuum chamber. The plasma potential distribution was measured by a Langmuir probe method to understand the effect of the substrate dc bias during hydrogen plasma cleaning. It changes from downhill to uphill distribution as the dc bias changes from a negative to a positive value, which leads to a decrease in the ion number density arriving at the substrate and results in the complete suppression of the defect formation in the Si substrate. In situ hydrogen plasma cleaned Si wafer always resulted in higher quality epilayers than ones cleaned only by so‐called hydrogen passivation after the HF dip. We found that there is a critical dose of the hydrogen ions during in situ plasma cleaning beyond which crystalline defects are observed in the Si substrate, subsequently leading to the poor crystallinity of the epilayers. The dose of...

Amorphous {100} platelet formation in (100) Si induced by hydrogen plasma treatment

The defect formation in (100) Si at low temperatures during electron cyclotron resonance hydrogen plasma treatment has been studied. The temperature effect on crystalline defect morphology is studied by transmission electron microscopy and high resolution transmission electron microscopy. A high density of hydrogen-stabilized {111} platelets is observed at 240 °C, whereas a large number of amorphous {100} platelets is observed at 385 °C. The formation of amorphous {100} platelets without {111} platelets at 385 °C is reported. The amorphous {100} platelet at 385 °C results from the precipitation of oxygen promoted by hydrogen-enhanced oxygen diffusion. The low-temperature photoluminescence study and the spreading resistance profiles for the hydrogenated Si support the proposed mechanism of the amorphous {100} platelet.

Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash

We have investigated thin film transistors (TFTs) with ultra-thin polycrystalline silicon (poly-Si) of 77 Å – 185 Å. The TFT charge transfer characteristics such as ON current and effective mobility are dominated not by the thickness itself but by the grain size of poly-Si channel. When the poly-Si channel thickness is decreased with the same grain size, the sub-threshold TFT characteristics are improved without degradation of ON current and reliability properties. These results give us appropriate criteria to establish an excellent poly-Si channel in vertical NAND flash memory.

Highly functional and reliable 8Mb STT-MRAM embedded in 28nm logic

We fabricated 8Mb 1T-1MTJ STT-MRAM macro embedded in 28nm CMOS logic platform by developing novel integration/stack/patterning technologies. MTJ memory cell array was successfully embedded into Cu backend without open fail and severe degradation of magnetic property. Advanced perpendicular MTJ stack using MgO/CoFeB was developed to show high TMR value of 180% after full integration. In addition, ion beam etching (IBE) process was optimized with power, angle, and pressure to reduce a short fail below 1 ppm. Through these novel technologies, we demonstrated highly functional and reliable 8Mb eMRAM macro having a wide sensing margin and strong retention property of 85 0C and 10yrs.

A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond

A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and excellent co-integration feasibility. A Strain-Relaxed SiGe Buffer (SRB) layer is introduced as buried stressor and successfully transfers up to ∼1 GPa uniaxial tensile and compressive stress to the Si/SiGe n-/p-channels simultaneously. As the result, both tSi and cSiGe devices show a 40% and 10% electron and hole mobility gain over unstrained Si, respectively. Through a novel gate stack solution including a common interfacial layer (IL), HK, and single metal gate for both n- and pFET, secured process margin for 5nm gate length, low interface trap density (Dit) for SiGe channel and threshold voltage (Vt) target for both the Si and SiGe device are successfully demonstrated. Lastly, reliability investigation shows that tSi and cSiGe, employing the newly developed common gate stack scheme, possess superior reliability characteristics compared with those of equivalent Si devices.

Low temperature in situ boron doped Si epitaxial growth by ultrahigh vacuum electron cyclotron resonance chemical vapor deposition

Boron-doped silicon epitaxial layers were grown by ultrahigh vacuum electron cyclotron resonance chemical vapor deposition at 440–510 °C. Reflection high-energy electron diffraction and transmission electron microscopy (TEM) were used to study the effect of boron doping on the crystalline quality of silicon epitaxial layers. At growth conditions where undoped defect-free Si epitaxial layers were successfully obtained at 440 °C, in situ boron-doped epitaxial layers were replete with twins. However, at conditions with increased ion energy flux and at a higher temperature, 470 °C, no twins were observed. TEM analysis revealed the presence of an amorphous phase in the twinned epitaxial layers. It is believed that the amorphous phase formation, presumably from the reaction between B and O during the doping process, appeared to hinder the growth of the epitaxial layer, leading to degradation of the Si crystalline quality. Defect-free boron-doped Si epitaxial layers were able to be obtained by suppressing the am...

In situ boron doping of Si and Si1−xGex epitaxial layers by ultrahigh vacuum electron cyclotron resonance chemical vapor deposition

We report on the growth of in situ boron doped Si and Si1−xGex epitaxial layers at 510 °C by ultrahigh vacuum electron cyclotron resonance chemical vapor deposition. Boron concentration increases with B2H6 partial pressure. The boron concentration decreases as microwave power increases in Si epilayers and as Ge fraction increases in Si1−xGex epilayers. Enhanced ion bombardment at these conditions promotes the desorption of boron hydride in the growth surface. No growth rate change is observed in the Si epilayer with B2H6 partial pressure. However, a significant growth rate decrease is observed for the Si1−xGex epilayer with B2H6 partial pressure.We report on the growth of in situ boron doped Si and Si1−xGex epitaxial layers at 510 °C by ultrahigh vacuum electron cyclotron resonance chemical vapor deposition. Boron concentration increases with B2H6 partial pressure. The boron concentration decreases as microwave power increases in Si epilayers and as Ge fraction increases in Si1−xGex epilayers. Enhanced ion bombardment at these conditions promotes the desorption of boron hydride in the growth surface. No growth rate change is observed in the Si epilayer with B2H6 partial pressure. However, a significant growth rate decrease is observed for the Si1−xGex epilayer with B2H6 partial pressure.

Advanced Si solid phase crystallization for vertical channel in vertical NANDs

The advanced solid phase crystallization (SPC) method using the SiGe/Si bi-layer structure is proposed to obtain high-mobility poly-Si thin-film transistors in next generation vertical NAND (VNAND) devices. During the SPC process, the top SiGe thin film acts as a selective nucleation layer to induce surface nucleation and equiaxial microstructure. Subsequently, this SiGe thin film microstructure is propagated to the underlying Si thin film by epitaxy-like growth. The initial nucleation at the SiGe surface was clearly observed by in situ transmission electron microscopy (TEM) when heating up to 600 °C. The equiaxial microstructures of both SiGe nucleation and Si channel layers were shown in the crystallized bi-layer plan-view TEM measurements. Based on these experimental results, the large-grained and less-defective Si microstructure is expected to form near the channel region of each VNAND cell transistor, which may improve the electrical characteristics.