Bong-Joon Lee

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A variable-interval oversampling clock/data recovery circuit (CDR) provides robust operation under varying jitter conditions. An eye-measuring loop in the CDR enables data recovery at maximum eye-opening, responding to the amount and shape of jitter. The CDR in 0.25 /spl mu/m CMOS shows <10/sup -13/ BER for 2/sup 7/-1 PRBS (pseudo-random-bit-sequence) at 5GBaud.

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

A 20-GHz phase-locked loop with 4.9 ps/sub pp//0.65 ps/sub rms/ jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-/spl mu/m CMOS operates from 17.6 to 19.4GHz and dissipates 480mW.

A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization

A 2.5 to 10 Gb/s CMOS transceiver in 0.18 /spl mu/m CMOS dissipates 540 mW from a 1.8 V supply with a BER better than 10/sup -12/. CDR loop characteristics are stabilized across various jitter environments with small hardware overhead using an alternating edge sampling phase detector.

Design Optimization of On-Chip Inductive Peaking Structures for 0.13-

This paper describes design methodologies for the optimal inductive peaking structures used for the 40-Gb/s serializing transmitter circuits presented in. The implemented transmitter had more than 400 on-chip inductors and transformers in order to achieve the bandwidth required for the 38.4-Gb/s operation demonstrated in a 0.13-μm CMOS process. A bridged T-coil network with inverted mutual coupling was found more effective than the conventional T-coil with sizeable driver-side capacitance. An iterative refinement procedure that directly optimizes the circuits large-signal transient response at the presence of the inductor parasitics and device nonlinearities via HSPICE-ASITIC joint-simulation is described. The procedure resulted in more than 3 × improvement in bandwidth for the CML buffer, multiplexer, and latch circuits. It is shown that the area and the achievable bandwidth of the optimal inductive peaking structures will scale favorably with the CMOS technology trends.

\mu{\hbox {m}}

Implemented in 0.13/spl mu/m CMOS, the 40Gb/s transmitter uses shunt-and-double-series inductive peaking and negative feedback for bandwidth enhancement and pulsed latch-based dividers and retimers for timing closure. The 38.4Gb/s 2/sup 31/-1 PRBS transmitted eye has differential voltage swing of 549mV/sub pp/, rise time of 14ps, and clock jitter of 0.65/sub rms/ and 4.9/sub pp/.

CMOS 40-Gb/s Transmitter Circuits

We describe photopatterning technique that employs the photodegradation of cell-adhesive-modified poly(ethyleneimine) (m-PEI) to fabricate precise micropatterns on the indium tin oxide (ITO) substrate for guided neuronal growth. The photodegradation of m-PEI coated on hydroxyl group-terminated ITO substrate created micropatterns over a large area through deep UV irradiation. The photopatterned m-PEI layer can effectively guide neurite outgrowth and control neurite extensions from individual neurons.

Circuit techniques for a 40Gb/s transmitter in 0.13/spl mu/m CMOS

A low-power, single-channel clock-edge modulated serial link has been fabricated in a standard 0.18-mum CMOS technology. The link core size is 343 times 188 mum2 for the transmitter and 173 times 83 mum2 for the receiver. The link consumes 3.12 mW when operating at 270 Mb/s with a 1.2-V supply. The proposed link transfers all necessary signals between a graphic processor and a mobile display device over a single pair channel, thereby greatly saving the power and cost of the existing full swing parallel lines. The proposed clock edge modulation (CEM) encoding can keep the channel DC-balanced without an additional bit overhead. Since a clock edge is present for each bit, an external reference clock is not needed and its operating frequency can be varied without the possibility of harmonic locking typically found in a referenceless clock and data recovery circuit. A simple DLL-based CEM decoder is described that recovers the data with low power consumption and high jitter tolerance. An analysis of the jitter tolerance to sinusoidal jitter is included along with measured data. The measurement results show jitter tolerance of 20 UIP-P with 1-MHz sinusoidal jitter. The use of a push-pull voltage-mode driver further reduces the power consumption.

Photopatterning of cell-adhesive-modified poly(ethyleneimine) for guided neuronal growth.

A 20GHz phase-locked loop with 4.9ps/sub pp//0.65ps/sub rms/ jitter and -101.2dBc/Hz phase noise at 1MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled-microstrip resonator. Static frequency dividers made of pulsed latches operate faster than a flip-flop based divider and achieve near 2:1 frequency range. The PLL fabricated in 0.13/spl mu/m CMOS operates from 17.6GHz to 19.4GHz and dissipates 480mW.

A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme

This paper describes the design and the implementation of a fully integrated 10 Gb Ethernet transceiver in a 0.13-/spl mu/m CMOS process using only a 1.2 V supply. A coarse control algorithm that combines a voltage range monitoring circuit with a frequency lock detector provides a robust operation against process, voltage, and temperature (PVT) variations for a VCO with a ring oscillator. With the use of a blind oversampling DPLL architecture, four channels of XAUI transceivers can share a single PLL, eliminating the clock synchronization problem between channels. Also, the total number of clock domains for the entire chip is reduced to three, making the integration of the XAUI with the 10G transceiver much simpler. The test chip consumes 898 mW from a 1.2 V supply.

A 20-GHz phase-locked loop for 40Gb/s serializing transmitter in 0.13/spl mu/m CMOS

This paper describes a quad 3.125 Gbps transceiver focusing on digital data recovery circuits. Effect of each design parameters on jitter tolerance (JTOL) is analyzed and for better JTOL, a new phase-averaging method with internal forward path is proposed. On-chip JTOL measurement circuits are implemented to characterize the transceiver performance, and it shows that the proposed method improves the JTOL about 0.1 UI. Implemented in 0.13 CMOS, the transceiver tolerates up to 0.67 UI of total jitter at 3.125Gbps.