Jeong-Kyoum Kim

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

A Fully Integrated 0.13-

A fully integrated 40-Gb/s transceiver fabricated in a 0.13-mum CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low fTof 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4 times 2.9 mm2 with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 215 -1 PRBS data is 1.85 psrms over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 psrms and the measured BER of the transceiver is less than 10- 14 .

\mu

A 20-GHz phase-locked loop with 4.9 ps/sub pp//0.65 ps/sub rms/ jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-/spl mu/m CMOS operates from 17.6 to 19.4GHz and dissipates 480mW.

m CMOS 40-Gb/s Serial Link Transceiver

This paper describes design methodologies for the optimal inductive peaking structures used for the 40-Gb/s serializing transmitter circuits presented in. The implemented transmitter had more than 400 on-chip inductors and transformers in order to achieve the bandwidth required for the 38.4-Gb/s operation demonstrated in a 0.13-μm CMOS process. A bridged T-coil network with inverted mutual coupling was found more effective than the conventional T-coil with sizeable driver-side capacitance. An iterative refinement procedure that directly optimizes the circuits large-signal transient response at the presence of the inductor parasitics and device nonlinearities via HSPICE-ASITIC joint-simulation is described. The procedure resulted in more than 3 × improvement in bandwidth for the CML buffer, multiplexer, and latch circuits. It is shown that the area and the achievable bandwidth of the optimal inductive peaking structures will scale favorably with the CMOS technology trends.

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

A referenceless, continuous-rate, fast-locking CDR with an operating range of 180 Mb/s to 3.2 Gb/s is presented. The harmonic lock property of a rotational frequency detector and the maximum run-length limit of 8B10B encoded data are utilized to detect a harmonic lock and to accelerate acquisition process. A separate VCO control scheme is introduced to stabilize the loop with a modest amount of on-chip capacitance.

Design Optimization of On-Chip Inductive Peaking Structures for 0.13-

Implemented in 0.13/spl mu/m CMOS, the 40Gb/s transmitter uses shunt-and-double-series inductive peaking and negative feedback for bandwidth enhancement and pulsed latch-based dividers and retimers for timing closure. The 38.4Gb/s 2/sup 31/-1 PRBS transmitted eye has differential voltage swing of 549mV/sub pp/, rise time of 14ps, and clock jitter of 0.65/sub rms/ and 4.9/sub pp/.

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A 20GHz phase-locked loop with 4.9ps/sub pp//0.65ps/sub rms/ jitter and -101.2dBc/Hz phase noise at 1MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled-microstrip resonator. Static frequency dividers made of pulsed latches operate faster than a flip-flop based divider and achieve near 2:1 frequency range. The PLL fabricated in 0.13/spl mu/m CMOS operates from 17.6GHz to 19.4GHz and dissipates 480mW.

CMOS 40-Gb/s Transmitter Circuits

A fully integrated 40-Gb/s transceiver is implemented in a 0.13-mum CMOS technology. This paper describes the challenges in designing a 20-GHz input sampler, a 20-GHz quadrature LC-VCO, a 20-GHz bang-bang phase detector, and a 40-Gb/s equalizer. The transceiver occupies 1.7 times 2.9 mm2 and dissipates 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 215-1 PRBS data is 1.85 psrms over a wire-bonded plastic ball grid array (PBGA) package, an 8-mm RO-4350B PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable, while the recovered clock jitter is 1.77 psrms. The measured BER is < 10-14.

A 180-Mb/s to 3.2-Gb/s, continuous-rate, fast-locking CDR without using external reference clock

This paper presents 20-Gb/s full-rate 27-1 PRBS generator with 20-GHz PLL. Implemented in a 0.13-mum CMOS process with fT of only about 80 GHz, the proposed PRBS core achieves 20-Gb/s full-rate by using pulsed latches instead of flip-flops and XOR gates with inductive peaking and negative feedback. The clock buffers that drive the 20-GHz clock distribution and the pulsed-latches in the PRBS core also employ single-transformer based inductive peaking and negative feedback to achieve bandwidth of 73 GHz. The measured data jitter of the 18.8-Gb/s PRBS output is 2.78 psrms and 14.4 pspp. The measured clock jitter of the divided-by-16 clock is 1.99 psrms and 14.4 pspp. The fabricated PRBS generator and PLL dissipate 0.84 W and 0.17 W, respectively, from a 1.5-V supply.

Circuit techniques for a 40Gb/s transmitter in 0.13/spl mu/m CMOS

This paper presents a frequency divider with a wide operating frequency range and a high bandwidth CML buffer intended for an 80-Gb/s serial link system. The proposed divider uses a pulsed-latch architecture that replaces the slave latch in a flip-flop-based divider with a buffer. The CML buffer employs both shunt-and-double-series inductive peaking and active feedback. Implemented in a 0.13-mum CMOS process with fT of only 82 GHz, the divider operates over a wide range of 26.5-37.S GHz with an input sensitivity of 1 Vpp, diff and produces a nominal output swing of 1 Vpp, diff. The CML buffer achieves a -3 dB bandwidth of 73.5 GHz in simulation, which is high enough to buffer an 80-Gb/s NRZ data stream. The fabricated frequency divider and clock buffers dissipate 22.5 mW and 72 mW, respectively, from a 1.8-V supply.